This video is the inaugural broadcast of “Women in Tech Works,” a new initiative by Tech Works dedicated to raising awareness, promoting, celebrating, and accelerating women’s careers across the UK tech sector, including semiconductors, AI, and cybersecurity.

It features Rasadhi Attale, a Senior Hardware Engineer at Siemens, who presents on “Scalable Verification for Systems on Chip (SoCs): Managing Complexity at Scale.” Raz, also pursuing a Master’s in Cybersecurity at Oxford, brings extensive experience from her previous work at ARM on Cortex-A processors. Key topics from her presentation include:

• Distinguishing Test from Verification: While “test” identifies physical issues post-fabrication, “verification” ensures a design is correctly implemented according to specifications throughout the design phase.

• Verification Challenges: Complex designs with billions of transistors, large verification state spaces, multiple interfaces, cross-domain complexities, slow simulations, and limited computing resources.

• Scalable Verification Framework: Emphasizes a hierarchical approach (block, subsystem, system level), reusable IPs/common components, scoreboards, checkers, coverage, and frequent regressions to monitor design health.

• Metric-Driven Verification (MDV): Quantifies verification status, clarifies completion criteria, identifies bugs early, and provides high confidence in code. Key components include test plans traceable to specifications and real-time, interactive dashboards for immediate visibility and trend analysis.

• Coverage: Discusses both functional and code coverage, using a waiver system for parameterized IPs and merged coverage from different configurations to optimize effort and confirm verification success.