Modern electronics depend on a semiconductor supply chain that spans dozens of countries, fabs, and third-party IP vendors. A single chip may pass through design houses, foundries, packaging facilities, and distributors before reaching a finished product. Each handoff is a potential entry point for compromise — counterfeit parts, cloned devices, malicious hardware Trojans inserted during fabrication, or recycled chips relabelled as new. Unlike software vulnerabilities, hardware flaws are baked into silicon and often invisible until a device is deployed in the field, making detection and remediation extraordinarily difficult and costly.

This is where hardware-based security anchors become essential. A Root of Trust (RoT) is a dedicated, tamper-resistant hardware block that establishes a trusted foundation for the entire system — verifying boot firmware, managing cryptographic keys, and ensuring that only authenticated code executes. Because it lives in silicon rather than software, an RoT is far harder to spoof or bypass than a purely software-based security layer.

Silicon identity complements this by giving each chip a unique, unclonable fingerprint — often derived from physical unclonable functions (PUFs) that exploit natural manufacturing variations. This identity allows a chip to be authenticated at every stage of its lifecycle, from fab to field, enabling provenance tracking and flagging counterfeits or unauthorized modifications.

Together, Root of Trust and silicon identity shift security left — embedding trust at the point of manufacture rather than bolting it on afterward. As supply chains grow more global and complex, these hardware-rooted defences are becoming not just best practice, but a baseline requirement for critical infrastructure, defence, and consumer electronics alike.

Chiiplet based design – is causing the shift from monolithic dies to chiplet-based design is reshaping semiconductor economics — and, in the same stroke, reshaping semiconductor trust.

A monolithic SoC has one manufacturer, one mask set, and one point of accountability. A chiplet package is a federation: compute tiles, I/O dies, and memory stacks sourced from different fabs, different process nodes, and sometimes different countries, assembled by a third party through advanced packaging like 2.5D interposers or 3D stacking. Each interface between dies is a new attack surface. Each sourcing decision is a new place where a counterfeit, recycled, or maliciously modified die could enter the supply chain undetected.

This disaggregation breaks some traditional assumptions DFT and security engineers relied on. Provenance can no longer be verified at the package level alone — each chiplet needs its own verifiable identity. That’s pushing adoption of die-level Root of Trust and PUF-based silicon identity, so every tile can cryptographically attest to its origin before it’s bonded into a package. Standards like UCIe are starting to bake authentication into the die-to-die interconnect itself, rather than treating security as a package-level afterthought.

The upside is real: chiplets let known-good dies be tested and screened independently before integration, arguably improving traceability compared to opaque monolithic supply chains. The challenge is that this only holds if every player in the ecosystem — foundry, OSAT, integrator — implements attestation consistently. Chiplet security is ultimately a supply chain coordination problem as much as a technical one.

siemens.com