Accelerating Chiplet SoC Development with Standards-Based Frameworks and Automated Design Flows

As AI systems increase demand for high-performance and power-efficient silicon, chiplet architectures provide a scalable path to heterogeneous integration. This presentation introduces the Cadence Chiplet Framework, supporting Arm CSA, OCP FCSA, and UCIe standards, with pre-verified subsystems for control, security, safety, and debug. It also highlights SoC Cockpit, an automation platform using AI-assisted techniques to streamline development from architecture through RTL, verification, and implementation. Together, these technologies reduce engineering effort, accelerate development, and improve interoperability for complex multi-die SoC designs.

Biography

Derek McAulay is a Design Engineering Architect at Cadence with over 20 years of experience in semiconductor IP and SoC development. He is a technical leader in chiplet-based system design and architecture and has played a key role in the delivery, tape-out, and bring-up of Cadence’s first base system chiplet. His expertise spans high-speed interfaces including UCIe, CXL, PCIe, and MIPI, as well as RTL design, emulation, and system-level validation. Derek focuses on scalable chiplet architectures and design automation to accelerate development of next-generation silicon systems.