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DTSTART;VALUE=DATE:20260714
DTEND;VALUE=DATE:20260715
DTSTAMP:20260630T134527Z
CREATED:20260630T134527Z
LAST-MODIFIED:20260630T134527Z
UID:8207-1783987200-1784073599@techworks.org.uk
SUMMARY:Scaling Compute Connectivity with PCIe and CXL: Chip-to-Chip and Emerging Architectures
DESCRIPTION:
URL:https://www.synopsys.com/webinars/compute-connectivity-pcie-cxl-architectures.html?utm_source=techworks&utm_medium=link&utm_campaign=hpcip&utm_content=compute-connectivity-pcie-cxl-wbr_link_mul_wbn&tags=Webinars#new_tab
LOCATION:Webinar
CATEGORIES:Member Event,past-events
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/06/NEW-Techworks-site-featured-images-2026-06-30T144021.706.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260708T090000
DTEND;TZID=Europe/London:20260708T170000
DTSTAMP:20260608T131707Z
CREATED:20260608T131707Z
LAST-MODIFIED:20260608T131707Z
UID:7843-1783501200-1783530000@techworks.org.uk
SUMMARY:Cambridge Wireless Technology & Engineering Conference 2026
DESCRIPTION:Following its landmark 10th anniversary in 2025\, the CW Technology and Engineering Conference (CWTEC) continues as a key fixture in the UK tech calendar. Each year\, the conference brings together 250+ senior engineers\, technologists\, academics\, and business leaders to tackle the most pressing technology challenges shaping our economic future. \nIn July 2026\, CWTEC turns its focus to the semiconductor and photonics technologies shaping the next decade of connectivity and compute. \nAs the semiconductor industry accelerates into an era defined by AI\, electrification\, and advanced connectivity\, the engineering challenges are becoming more complex than ever. Miniaturisation is no longer the sole driver of technological advances. Speed\, heat\, bandwidth\, and\, most importantly\, energy efficiency\, are driving us to think and innovate differently. \nCWTEC 2026 will explore how the UK’s semiconductor and photonics landscape is evolving to meet these challenges. At the conference\, we will take a deeper technical look at the semiconductor and photonics technologies that are shaping today’s AI boom\, and we will look to the future\, to the technologies that will shape the next decade. \n\nWhere are we now\, in design\, manufacturing\, materials and systems integration?\nAnd what must evolve to meet future demands in connectivity\, energy efficiency\, quantum\, sensing and high-performance compute?\nWhat new bottlenecks are emerging?\nAnd critically\, where can the UK carve out distinctive global leadership?\n\nThe UK is internationally recognised in semiconductors and photonics and has strategically important strengths. As traditional scaling slows and system-level innovation becomes the differentiator\, the UK’s capabilities matter more than ever. \nHow do we capitalise on this unique opportunity? And where should the UK take a lead? \nBringing together engineers\, technologists\, and industry leaders\, the event will provide technically rigorous insight\, forward-looking debate\, and practical perspectives on what comes next. \nIf you’re working at the frontier of semiconductor and photonics innovation in the UK\, this is where the next chapter gets shaped. \nThis year’s agenda will focus on four areas:  \n\nUK Strengths\, Capabilities & GapsAs the semiconductor industry looks to move beyond the current AI wave\, this session assesses the UK’s current position in the globally competitive semiconductor ecosystem: our strengths\, our gaps\, and the opportunities that lie ahead. With a focus on what comes next – from photonics and power electronics to heterogenous integration – we will explore how the UK can shape and lead in the next frontier of technology.\nPower Electronics\, Photonics and Quantum – Does the Past Dictate the Future?Are the performance gains still sufficient to justify further investment? With R&D taking place across a range of semiconductor materials\, how will material choices be made\, and which are ultimately likely to succeed in the market? This could span CS\, 2D materials and rare earth metals for semiconductors\, devices\, interposers\, substrates\, gratings and heatsinks. How will this expertise help accelerate and support quantum solutions?\nDesign & Future Compute ArchitecturesWhile AI dominates headlines\, compute innovation is diversifying. Distinct markets are emerging for data centre training\, inference\, and edge computing\, each requiring specialised solutions. Beyond AI\, we are seeing a resurgence in CPU innovation and ultra-low latency optical architectures\, while quantum computing nears commercial viability. The UK is well-positioned to lead\, boasting a rich history of innovation and over 200 semiconductor design teams. The challenge lies in leveraging these domestic strengths within a global landscape currently controlled by a few massive vendors and customers.\nSovereign Supply ChainsExport controls\, trade barriers\, geopolitical tensions and competition for critical materials are changing where and how semiconductor and photonic supply chains work. The UK has world class capabilities in chip design\, compound semiconductors and photonics\, but where are the real bottlenecks in delivering on those strengths at scale\, particularly for critical applications like AI\, data centres and high performance compute? Does the UK have the domestic capacity to match its ambitions\, or does it need the right partnerships to bridge the gap?
URL:https://techworks.org.uk/event/cambridge-wireless-technology-engineering-conference-2026/
LOCATION:30 Euston Square\, 30 Euston Square\, London\, NW1 2FB
CATEGORIES:past-events,Promoted
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/06/NEW-Techworks-site-featured-images-2026-06-08T141437.352.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260707
DTEND;VALUE=DATE:20260708
DTSTAMP:20260701T102523Z
CREATED:20260626T161344Z
LAST-MODIFIED:20260701T102523Z
UID:8137-1783382400-1783468799@techworks.org.uk
SUMMARY:BICS and how to manage rising energy costs
DESCRIPTION:Join Envantage\, for an exclusive webinar for TechWorks members on BICS\, and how to manage rising energy costs.\nIn this session we’ll cover: \n– What BICS means for UK businesses and what to expect for your business\n– How electricity and gas bills are really structured\n– Why network and non-commodity charges have risen so much in 2026 and are expected to continue increasing in the coming years\n– How you can manage and reduce these costs\n– Tariff structure and charging bands: What they are\, whether you can change them\n– Exemptions and compensation schemes including BICS\, EII\, NCC\, and CCA\n– Energy purchasing strategies: Different ways to buy power and how removing non-commodity charges can significantly reduce your overall bill \nIf you’re responsible for energy\, sustainability or procurement in your organisation\, this webinar will give you the information you need\, to make informed decisions. \nWhether your organisation is directly affected by BICS or looking to control rising energy costs\, Envantage’s experts will give you practical insights and clear next steps. \nSpeakers: \n– Jessica Harris – Senior Energy & Carbon Consultant. Jessica has been with Envantage for 18 years\, and is responsible for leading the relationship with TechWorks\, alongside many of the company’s most important relationships. She has a deep understanding of the benefits available to businesses from a complete range of energy services\, across many sectors. \n– Michael Holness – Senior Energy & Carbon Consultant. Working in the energy consultancy sector for over 10 years\, Michael brings a wealth of experience around energy compliance\, and the interplay between all the exemption and compensation schemes available to UK manufacturers. \n– Rachel Hulme – Energy & Carbon Consultant. Rachel has responsibility for Envantage clients\, providing ongoing support to maximise the savings associated with energy compliance.
URL:https://techworks.org.uk/event/bics-and-how-to-manage-rising-energy-costs/
LOCATION:Webinar
CATEGORIES:Partnered,past-events,Webinar
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/06/NEW-Techworks-site-featured-images-2026-07-01T112357.659.webp
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260701T120000
DTEND;TZID=Europe/London:20260701T130000
DTSTAMP:20260616T083419Z
CREATED:20260615T161508Z
LAST-MODIFIED:20260616T083419Z
UID:7960-1782907200-1782910800@techworks.org.uk
SUMMARY:Promoted Event: Rethinking Neuroinclusion
DESCRIPTION:
URL:https://keap.page/qjf592/rethinking-neuroinclusion.html#new_tab
LOCATION:Webinar
CATEGORIES:past-events,Webinar,Women in TechWorks
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/06/NEW-Techworks-site-featured-images-2026-06-15T171031.582.webp
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260625T160000
DTEND;TZID=Europe/London:20260625T163000
DTSTAMP:20260423T092958Z
CREATED:20260309T145703Z
LAST-MODIFIED:20260423T092958Z
UID:5966-1782403200-1782405000@techworks.org.uk
SUMMARY:Women in TechWorks: Fireside Chat with Farah Comis\, CEO of Altro Photonics
DESCRIPTION:Farah Comis is the CEO of Altro Photonics.  She completed her PhD in the Optical Networks Group at University College London (UCL)\, supervised by Dr. Alfonso Ruocco. She holds an MEng in Electronic and Electrical Engineering from UCL and an MRes in Connected Electronic and Photonic Systems from the University of Cambridge. \nHer PhD thesis\, Integrated Photonic Platforms for Next-Generation Optical Transmitters\, focused on integrated photonics using high-index-contrast platforms including silicon nitride on insulator (SiNOI) and lithium niobate on insulator (LNOI). She developed state-of-the-art silicon and lithium-niobate modulators and quantum devices\, resulting in first-author publications in Optics Express and Optics Letters\, a patent filing\, and presentations at IEEE Silicon Photonics and CLEO\, as well as an invited talk at the CORNERSTONE User Day. \nAlongside her research\, Farah is spinning out technology from UCL into a spin-out. She is part of the Future Worlds accelerator and previously participated in the 50:50 program backed by 50 Years VC\, supporting the commercialisation of an integrated photonics platform.
URL:https://techworks.org.uk/event/women-in-techworks-fireside-chat-with-farah-comis-ucl/
LOCATION:Webinar
CATEGORIES:past-events,TechWorks,Women in TechWorks
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/03/NEW-Techworks-site-featured-images-2026-03-09T144927.847.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260625
DTEND;VALUE=DATE:20260626
DTSTAMP:20260608T162551Z
CREATED:20260608T162551Z
LAST-MODIFIED:20260608T162551Z
UID:7860-1782345600-1782431999@techworks.org.uk
SUMMARY:Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools
DESCRIPTION:
URL:https://www.synopsys.com/webinars/intel-emib-design-advanced-ai-datacenter-solutions.html?utm_source=techworks&utm_medium=link&utm_campaign=mds&utm_content=intel-emib-t-wbnr_link_mul_wbn&tags=Webinars#new_tab
LOCATION:Webinar
CATEGORIES:Member Event,past-events,Webinar
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/06/synopsys-intel-webinar-1200x1200-1.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260624
DTEND;VALUE=DATE:20260625
DTSTAMP:20260617T151456Z
CREATED:20260617T151329Z
LAST-MODIFIED:20260617T151456Z
UID:8046-1782259200-1782345599@techworks.org.uk
SUMMARY:Synopsys Virtual Prototyping Day
DESCRIPTION:
URL:https://www.synopsys.com/events/virtual-prototyping-day.html?utm_source=techworks&utm_medium=link&utm_campaign=ns&utm_content=virtual-prototyping-day-26_link_mul_wbn&tags=Webinars#new_tab
LOCATION:Webinar
CATEGORIES:Member Event,past-events
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/06/NEW-Techworks-site-featured-images-2026-06-17T160916.597.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260623T080000
DTEND;TZID=Europe/London:20260623T170000
DTSTAMP:20260316T143159Z
CREATED:20260316T143104Z
LAST-MODIFIED:20260316T143159Z
UID:6057-1782201600-1782234000@techworks.org.uk
SUMMARY:Join TechWorks at VF2026 – UK’s Premier Verification & Semiconductor Event!
DESCRIPTION:
URL:https://www.tessolve.com/verification-futures/vf2026-uk/#new_tab
CATEGORIES:past-events,Promoted,TechWorks
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/03/NEW-Techworks-site-featured-images-2026-03-16T142852.136.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260618T080000
DTEND;TZID=Europe/London:20260618T170000
DTSTAMP:20260618T133444Z
CREATED:20260618T132536Z
LAST-MODIFIED:20260618T133444Z
UID:8063-1781769600-1781802000@techworks.org.uk
SUMMARY:Partnered Event: UK Silicon Carbide Network Conference 2026
DESCRIPTION:
URL:https://warwick.ac.uk/fac/sci/eng/engresearch/siliconcarbide/
CATEGORIES:Partnered,past-events,TechWorks
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/06/NEW-Techworks-site-featured-images-2026-06-18T142047.428.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260617T090000
DTEND;TZID=Europe/London:20260617T173000
DTSTAMP:20260615T155644Z
CREATED:20260212T160012Z
LAST-MODIFIED:20260615T155644Z
UID:5568-1781686800-1781717400@techworks.org.uk
SUMMARY:Women in TechWorks: Engineering Intelligently
DESCRIPTION:AgendaSpeakers and PanelJoin us for the first in-person Women in TechWorks event at Arm\, bringing together women and allies from across the semiconductor and technology ecosystem.CLICK HERE to find out more about Women in TechWorks\nCLICK HERE to find out how you can sponsor this event \nAs a growing network\, Women in TechWorks is dedicated to fostering connection\, mentorship\, visibility\, leadership\, and inclusion. Helping to create stronger pathways for women to develop and thrive in deep tech. \nWhile recognition is important\, meaningful progress happens through everyday actions: creating space for diverse voices\, challenging assumptions\, empowering talent to succeed\, and actively supporting one another as allies. \nFounded by Jillian Hughes together with the Women in TechWorks board\, the initiative was created to strengthen the sector’s talent pipeline through mentoring\, training\, and increased visibility for women across the industry. \nOur goal is to help women make a bigger\, more significant contribution to the sector’s prospects by attracting\, supporting\, and advancing them at each stage of their career path. \nThis event will also explore key topics shaping the industry today\, including artificial intelligence and the future of engineering. \nEvent Sessions\nMentoring \, Leadership and Retention – Are we moving the needle? \nWe are exploring a session focused on mentoring\, leadership\, and the retention of women in technology\, looking at what organisations are doing in practice to support progression and long-term careers for women in the sector. The discussion will consider how companies are building effective mentorship and sponsorship programmes\, developing leadership pipelines\, and creating inclusive cultures that enable women to thrive and progress. We are particularly interested in hearing how organisations are using data\, technology and emerging tools such as AI to identify gaps\, address barriers\, and create scalable pathways for advancement. Speakers would be invited to share practical insights\, lessons learned\, and reflections on whether current initiatives are truly shifting the needle in improving representation and retention of women in tech. \nTrends in the Workplace – Solving Complex Problems Using AI \nIndustry experts will share how engineers are using AI to analyse complex data\, accelerate innovation and unlock new approaches to technical challenges. The session will also highlight the contributions of women engineers in shaping these\, exploring how diverse perspectives can influence problem-solving\, innovation and the way complex technical challenges are approached. \nFrom Strategy to Systems: Executive Leadership in AI Era \nThis session will explore how organisations are moving beyond AI strategy to real-world implementation across technology\, teams and operations. We are particularly interested in hearing whether companies have successfully transitioned from planning to practical adoption\, what that journey has looked like\, and the challenges encountered along the way. The discussion will also consider the role of women leaders in shaping how AI is adopted and governed\, ensuring diverse leadership voices are represented in decisions that will define the future of AI-enabled organisations. \n  \nWhy attend\n\nConnect with women and allies from across the semiconductor and deep tech ecosystem.\nHear practical perspectives on leadership\, mentoring and career development.\nExplore how current trends such as AI are affecting engineering and progression.\nBe part of shaping a growing community focused on visibility\, inclusion\, and opportunity for women in tech.\n\nWhat you will take away\n\nNew connections across the ecosystem\nFresh perspectives on leadership and career development\nInsight into how AI is influencing engineering and workplace practices.\nA clearer sense of how Women in Techworks can support progression and visibility in the sector.\n\nJoin Us\nJoin us at Arm\, Cambridge for a day of knowledge sharing \, discussion and networking with leaders across the deep tech community. \nRegister now to secure your place and be part of the discussion shaping the future of engineering and leadership in the AI era. \nAgenda\n\n\n\n\nTime\nDetails\n\n\n\n\n09:00\nRegistration\n\n\n09:30\nOpening remarks Jillian Hughes\, Founder\, Women in TechWorks\n\n\n09:40\nDSIT – Task Force\n\n\n10:00\nKeynote Charlotte Eaton\, Chief People Officer\, Arm\n\n\n10:20\nMahdieh Ghoddusi\, Director of Delivery\, UKESF\n\n\n10:30\nNetworking Break Sponsored by Arm\n\n\n11:00\nMentoring \, Leadership and Retention – Are we moving the needle? – Hosted by Dr Becky Ellis\, Senior Manager Research Enablement\, Arm\n\n\n\nFrom Community to Competitive Advantage: The Power of Women’s ERGs in Tech Rachel Rees\, UK Committee Chair\,  Women@arm ERG\n\n\n\nEmpowering High performance teams Lee Harrison\, Marketing Director\, Siemens EDA\n\n\n\nSvetlana Grant\, Strategic Partnership Lead for Robotics\, Google DeepMind\n\n\n\nJanet Collyer MBE\, Portfolio Board Director and government advisor\n\n\n\nFrom Competent to Confident: What Actually Moves the Needle in Mentoring Women in Tech Dr Jan Peters MBE\, Director\, Katalytik\n\n\n\nInteractive Audience Discussion\n\n\n12:55\nNetworking Lunch\n\n\n13:55\nAI Trends in the workplace – Solving complex problems using AI – Hosted by Ras Attale\, Co-chair\, Women in TechWorks\n\n\n\nFrom Personal Knowledge Management to Augmented Cognition: Engineering the ‘Second Brain’ for AI-Enabled Technical Leadership Krishnapriya C.R.\, Senior Director of Engineering\, Arm\n\n\n\nEngineering AI Ethics-by-Design in Automotive: Standards & Regulations Dr Paula Palade\, AI Ethics Technical Specialist\, Jaguar Land Rover\n\n\n\nEngineering Innovation in RF Design: From Simulation Automation to AI-Driven Optimization Fatemeh Hoveizavi\, Business Development Manager\, EDRMEDESO\n\n\n\nPhysical AI: Unlocking intelligence to realise the Internet of Everything Catherine Ramsdale\, Senior Vice President Technology\, Pragmatic Semiconductor\n\n\n\nWhat the heck shall we do with the tech?! Julia Shalet\, Managing Director\, Product Doctor\n\n\n\nInteractive Audience Discussion\n\n\n15:50\nNetworking break\n\n\n16:20\nFrom Strategy to Systems: Executive Leadership in an AI Era\n\n\n\nPanel moderated by Helen Ledger\, Senior Vice President of Marketing\, Pragmatic Semiconductor Panellists: Caroline O’Brien\, CEO\, CSA Catapult Farah Comis\, CEO\, Altro Photonics Karima Dridi\, Head of Productivity Engineering\, CE-PE\, Arm Jen Walls\, CEO\, Clas-SiC\n\n\n17:00\nClosing Remarks\, Finish and networking\n\n\n19:00\nDrinks at Wilde Aparthotels\, Cambridge City Centre\n\n\n\n\n\n\n\n\n09:00\nRegistration\n09:30\nOpening remarks\nJillian Hughes\, Founder\, Women in TechWorks\n09:40\nDSIT – Task Force\n10:00\nKeynote\nCharlotte Eaton\, Chief People Officer\, Arm\n10:20\nMahdieh Ghoddusi\, Director of Delivery\, UKESF\n10:30\nNetworking Break Sponsored by Arm\n11:00\nMentoring\, Leadership and Retention – Are we moving the needle? – Hosted by Dr Becky Ellis\, Senior Manager Research Enablement\, Arm\n\nFrom Community to Competitive Advantage: The Power of Women’s ERGs in Tech\nRachel Rees\, UK Committee Chair\,  Women@arm ERG\n \nEmpowering High performance teams\nLee Harrison\, Marketing Director\, Siemens EDA\n \nSvetlana Grant\, Strategic Partnership Lead for Robotics\, Google DeepMind\n \nJanet Collyer MBE\, Portfolio Board Director and government advisor \nFrom Competent to Confident: What Actually Moves the Needle in Mentoring Women in Tech\nDr Jan Peters MBE\, Director\, Katalytik \nInteractive Audience Discussion \n12:55\nNetworking Lunch\n13:55\nAI Trends in the workplace – Solving complex problems using AI – Hosted by Ras Attale\, Co-chair\, Women in TechWorks\n\nFrom personal Knowledge Management to Augmented Cognition: Engineering  the ‘Second Brain’  for AI Enabled  Technical Leadership\nKrishnapriya C.R.\, Senior Director of Engineering\, Arm \nEngineering AI Ethics-by-Design in Automotive: Standards & Regulations\nDr Paula Palade\, AI Ethics Technical Specialist\, Jaguar Land Rover \nEngineering Innovation in RF Design: From Simulation Automation to AI-Driven Optimization\nFatemeh Hoveizavi\, Business Development Manager\, EDRMEDESO\n \nPhysical AI: Unlocking intelligence to realise the Internet of Everything\nCatherine Ramsdale\, Senior Vice President Technology\, Pragmatic Semiconductor\n \nWhat the heck shall we do with the tech?!\nJulia Shalet\, Managing Director\, Product Doctor \nInteractive Audience Discussion \n15:50\nNetworking break \n16:20\nFrom Strategy to Systems: Executive Leadership in an AI Era\n\nPanel moderated by Helen Ledger\, Senior Vice President of Marketing\, Pragmatic Semiconductor \nPanellists:\nCaroline O’Brien\, CEO\, CSA Catapult\nFarah Comis\, CEO\, Altro Photonics\nKarima Dridi\, Head of Productivity Engineering\, CE-PE\, Arm\nJen Walls\, CEO\, Clas-SiC\nJon Michaels\, Director\, microTECH \n17:00\n Closing Remarks\, Finish and networking\n19:00\nDrinks at Wilde Aparthotels\, Cambridge City Centre\n\n\n\nSpeakersDetailsDr. Paula PaladeAI Ethics Technical Specialist\, Jaguar Land Rover \n×Dr Paula Palade\nDr Paula Palade is an internationally recognised expert in AI ethics\, driving safety and ethical standards for connected and autonomous vehicles (CAVs) at Jaguar Land Rover\, as well as at European and global levels. With over a decade of experience in automotive engineering\, AI ethics\, and standardisation\, she has made substantial contributions to the International Standards Organisation (ISO) and the European Commission. Her mission is to ensure that AI is applied in a way that is ethical\, sustainable\, and beneficial to society.\nAs the AI Ethics Technical Specialist at Jaguar Land Rover\, Dr Palade leads the development and implementation of ethical principles and best practices for CAVs. Her academic background in electrical engineering includes a PhD\, multiple patents\, and publications in leading journals. She is deeply committed to using AI responsibly to improve lives across the automotive sector. Dr Palade’s work has earned her numerous accolades\, including Automotive Rising Star of the Year 2024 (US Detroit AutoTech)\, Top 50 Women in Engineering UK 2024\, and inclusion in the UK TechWomen100 and Autocar Top 100 Women in Automotive. She is also a strong advocate for diversity and inclusion in engineering\, serving as a STEM Ambassador\, Women in Engineering Mentor\, and Chartered Engineer mentor for the IET. She contributed to the European Commission’s report on the Ethics of CAVs\, providing 20 key recommendations shaping policy and legislation. Beyond her technical roles\, she regularly speaks at public events\, runs webinars on CAV safety\, and facilitates strategy for INCOSE and the IET.\nDetailsDr Jan Peters MBEDirector\, Katalytik \n×Jan Peters\n\nJan Peters is a globally recognised inclusion expert with over 25 years of experience combining a strong technical background in engineering with a focus on building diverse\, people-centred organisations. As director of Katalytik\, she has led influential research and developed practical tools to improve inclusion in engineering and construction\, while also contributing to higher education through programmes like UCL’s Integrated Engineering Programme and mentoring initiatives supporting over 1\,500 women. Her career spans industry\, academia\, and public policy\, and includes leadership roles such as President of the Women’s Engineering Society and recognition with an MBE in 2017. Her work is driven by a commitment to systemic\, evidence-based approaches to inclusion that deliver measurable impact. \nPresentation: From competent to confident: what actually moves the needle in mentoring women in tech \nThis talk explores why\, despite the growth of mentoring programmes for women in tech\, retention and progression remain stalled. Drawing on 25 years of experience and a decade of the WIBEC programme\, it argues that effective mentoring depends on structured design—careful matching\, trained mentors\, clear timeframes\, and shared frameworks like CliftonStrengths—but also highlights a deeper issue: a persistent confidence gap rather than a skills gap. It shows how systemic challenges such as unstable funding\, duplicated initiatives\, and lack of long-term investment undermine even well-designed schemes. While new tools\, including AI\, offer opportunities to scale impact\, the key message is that mentoring must be treated as a strategic\, evidence-based practice—not a “nice-to-have”—with proper resources\, coordination\, and commitment to truly support women’s progression in engineering and technology. \n\nDetailsJillian HughesHead of Semiconductors & DESN Network Director \n×Jillian Hughes\n\nJillian Hughes began her career with a recognised apprenticeship at National Semiconductor in Greenock\, Scotland\, completing her training in 1991. Over the next 15 years\, she built deep technical expertise in semiconductor equipment and process engineering\, working with major multinational companies including Seagate Microelectronics\, Motorola\, and Freescale Semiconductor. \nShe went on to lead operations across several specialised semiconductor businesses\, focusing on the manufacture\, refurbishment\, sale\, and service of high value capital equipment. \nIn April 2020\, Jillian was appointed NMI Director at Techworks\, the UK’s semiconductor trade association. In this role\, she drew on her extensive industry knowledge to support UK semiconductor companies and worked closely with industry and academia to raise the sector’s profile within Government. \nJillian later served as Chief Operating and Financial Officer at Dalrada Technology and Deposition Technology\, where she oversaw the development and manufacture of advanced capital equipment for emerging semiconductor markets. She has since returned to Techworks as Head of Semiconductors\, leading the Semiconductor Systems Design Network (DESN) and bringing together the UK’s dynamic chip design community to drive collaboration\, innovation\, and knowledge sharing. \nJillian also serves on the Board of Directors at Wafer Fab Solutions\, where she provides strategic business and financial guidance. \n\nDetailsLee HarrisonDirector of Product Marketing\, Tessent\, Siemens EDA \n×Lee Harrison\n\nLee Harrison is Director\, Product Marketing\, with Siemens Tessent Division. He has over 25 years of industry experience working with Siemens Tessent DFT products\, with a focus on safety and security. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC\, ITC\, VTS\, ETS\, and DATE. \n\nDetailsFatemeh HoveizaviBusiness development manager\, EDRMEDESO \n×Fatemeh Hoveizavi\n\nEngineering Innovation in RF Design: From Simulation Automation to AI-Driven Optimization \nThis talk presents a practical approach to accelerating engineering innovation in RF and antenna design through automation and emerging AI-driven methodologies. Using phased array antenna design as a case study\, I will demonstrate how Python-based workflows with PyAEDT can significantly streamline simulation processes\, reduce design cycles\, and improve reproducibility. \nThe session will highlight real-world engineering challenges in high-frequency system design and how automation enables more efficient exploration of complex design spaces. Building on this\, I will discuss how such workflows create a foundation for integrating AI and optimization techniques\, opening the door to smarter\, data-driven engineering practices. \nBeyond the technical aspects\, the talk will also reflect on the evolving role of engineers—where multidisciplinary skills\, adaptability\, and inclusive collaboration are key to building high-performing teams and delivering impactful solutions. \nThis presentation is aimed at engineers and technical leaders interested in bridging practical engineering workflows with emerging technologies such as AI\, while maintaining strong engineering fundamentals and best practices. \nBiography \nFatemeh Hoveizavi is a Technical Business Development Leader with over 15 years’ experience in electronic design\, simulation\, and advanced engineering systems. Holding a PhD in Telecommunications Engineering\, she specialises in electromagnetics\, RF/microwave engineering\, and semiconductor technologies. Working in the EDA sector\, she supports organisations across the full product lifecycle\, from concept to system-level verification\, solving complex challenges in areas such as PCB design\, IC/ASIC development\, and simulation. She bridges technical and business domains to drive technology adoption and growth. She also contributes to academia and actively promotes diversity\, supporting women pursuing careers in engineering and high-impact technology fields. \n\nDetailsCharlotte EatonChief People Officer\, Arm \n×Charlotte Eaton\n\nIn her role as Chief People Officer\, Charlotte oversees all aspects of Arm’s people\, workplace\, and sustainability strategies. Over the course of her career\, Charlotte has shaped her experience across multiple sectors with rapid adaptation and change\, and is passionate about building progressive\, inclusive\, purpose-led organizations. She thrives in seeking new ways of doing great things and inspiring others to think differently about the world of work while making it happen. \nBefore joining Arm\, Charlotte was Chief People Officer at OVO\, one of the UK’s largest energy companies\, focused on sustainability and renewable energy. In her role\, she was responsible for people\, property\, and customer experience. Prior to OVO\, Charlotte spent six years at Arm\, latterly as VP of People\, supporting teams in the Intellectual Property Group (IPG) globally. Before Arm\, Charlotte held HR leadership roles at The Heinz Company and worked at Barclays. Charlotte holds an LL.B. with first class honors. \n\nDetailsJulia ShaletManaging Director\, Product Doctor \n×Julia Shalet\n\nWhat the heck shall we do with the tech?! \nJulia “grew up” in a tech-driven industry. Her first job was as part of the launch team for the first mass market consumer mobile offering in the UK. Fast forward to now; countless new technologies later – for better and for worse – and the lessons remain the same. \nHow can we\, as individuals\, help our colleagues\, teams and organisations to cut through the hype and engineer intelligently. \nIn this talk\, Julia will give some practical models and examples to help us \n\nStay ahead & innovate whilst managing existing portfolios\nFocus on solving user problems and\nEnable a culture of learning as we need to discover what works and what doesn’t\n\nWe will have an opportunity to share stories from the coal-face\, consider what we have learned & take a moment to reflect on how we can be resilient\, responsive & adaptable. \nBiography \nJulia has built a career focused on maximising the real-world impact and commercial success of new technologies. From leading product strategy in the shift from 2G to 4G\, to scaling a Web 2.0 venture\, she has consistently worked at the forefront of innovation. Over the past decade\, she has helped established organisations transform through customer-centric\, product-led models. She also teaches innovation management at University College London and the Chartered Institute of Marketing. Her award-winning book The Really Good Idea Test has global reach\, and she has received multiple recognitions for her impact in innovation and entrepreneurship. \n\nDetailsMahdieh GhoddusiDirector of Delivery\, UKESF \n×Mahdieh Ghoddusi\n\nMahdieh Ghoddusi is Director of Delivery at the UK Electronics Skills Foundation\, where she leads the design and delivery of national initiatives that build the UK’s future electronics and semiconductor workforce. Working at the intersection of industry\, academia\, and government\, she develops high-impact approaches that strengthen early-career talent pipelines and address critical skills gaps across the sector. \nShe brings over 17 years of experience within a global technology organisation\, where she led programmes spanning early-career development and technical capability building for engineering teams. Her work included designing and delivering graduate and intern programmes\, as well as developing engineers across the business in emerging technologies and key industry domains\, including semiconductors. She also worked closely with universities through product-led engagement\, driving adoption of engineering tools and platforms. \nAt UKESF\, Mahdieh oversees a portfolio of activity spanning student development and outreach\, including initiatives such as Girls into Electronics\, which aim to broaden participation and inspire more young women to pursue pathways into engineering and technology. \nShe holds a BEng in Electronics Engineering from the University of Reading \n\nDetailsKrishnapriya C.RSenior Director of Engineering\, Arm  \n×Krishnapriya C.R \n\nKrishnapriya C.R is a Senior Director of Engineering at Arm Ltd\, UK\, where she leads the development of several strategic hardware products\, including cutting-edge AI systems. She has a strong track record of building and scaling high-performing teams to deliver innovative\, ground-up designs on time. Her organisation of over several hundred engineers spans Manchester\, Sheffield\, Cambridge\, Bristol\, Budapest (Hungary)\, and Bangalore (India). \nPrior to joining Arm\, Krishnapriya was Head of Product Definition at Infineon\, where she led the UK-based system architecture team for automotive microcontrollers. She brings deep hands-on experience across design\, verification\, and architecture development of IPs and SoCs\, combining technical expertise with a passion for building strong teams\, creating competitive products\, and helping engineers reach their full potential. \nShe is an advisory board member of Microelectronics UK\, and a strong advocate for applying AI across all aspects of R&D to improve efficiency and innovation\, and regularly shares her experience building AI-enabled software through webinars and in-person events. She is also an experienced mentor\, supporting engineers—particularly women—both within Arm and beyond. \n\nDetailsRachel ReesUK Committee Chair\, Women@arm ERG \n×Rachel Rees \n\nFrom Community to Competitive Advantage: The Power of Women’s ERGs in Tech \nWomen’s ERGs are no longer just support networks—they’re strategic drivers of business performance in the tech industry. \nThis presentation will show how they strengthen talent pipelines\, improve retention\, and accelerate leadership development through mentoring\, sponsorship\, and increased visibility of emerging talent. It will also highlight how ERGs provide critical insights into employee experience\, helping organisations remove barriers and build more inclusive cultures. \nAs technologies like AI reshape the industry\, we’ll explore how ERGs contribute to better decision-making and innovation by ensuring diverse perspectives are represented. \nUltimately\, this session makes the case for why Women’s ERGs are essential to building resilient\, competitive\, future-ready organisations. \nBiography \nRachel Rees is a Senior Licensing Manager at Arm\, working in the Partner Success and Licensing team and at the centre of the global semiconductor ecosystem\, where she helps to drive strategic partnerships enabling next-generation technologies. \nAlongside her commercial role\, she also chairs the Arm UK Women’s Employee Resource Group committee\, championing initiatives that advance inclusion\, strengthen talent pipelines and accelerate the progression of women in tech.\nWith over 20 years at Arm\, Rachel is a passionate advocate for mentoring and sponsorship\, and for translating inclusion into measurable impact. She brings a clear perspective on how diverse teams drive stronger innovation and better business outcomes and how building inclusive\, high-performing cultures can enable both individuals and organisations to thrive in a rapidly evolving technology landscape. \n\nDetailsCatherine RamsdaleSVP Technology\, Pragmatic Semiconductor  \n×Catherine Ramsdale\n\nPhysical AI: Unlocking intelligence to realise the Internet of Everything \nAI is only as powerful as the data it can access\, and today\, most of the physical world remains invisible. \nAs digital transformation accelerates\, the shift from the Internet of Things to the Internet of Everything is unlocking a new era of intelligence across consumer\, industrial\, healthcare and beyond. At the heart of this evolution are semiconductors\, enabling connectivity and compute across cloud\, edge and far edge – turning everyday objects into intelligent\, decision-making systems. \nHowever\, the semiconductor industry faces a range of unprecedented global challenges\, from supply chain constraints\, geopolitical uncertainties to sustainability challenges. These have all compounded to disrupt multiple industries\, delayed manufacturing and impacted economic growth. It’s also an imperative that we build for a solid future\, diverse talent pipeline\, where everyone can thrive in their careers. \nIt’s going to take a different approach to tackle these challenges\, diverging from established paradigms. That’s the approach that Pragmatic has taken. \nIn this session\, as part of the initial founding team at Pragmatic\, I’ll share how we are rethinking semiconductors\, and enabling physical AI through ultra-thin\, flexible\, and sustainable technology that enables intelligence where it previously wasn’t feasible\, or even possible. I’ll share some examples of how the technology is empowering physical AI and the tremendous opportunities this opens with possible future innovations. \nAlongside this\, I’ll reflect on my personal journey from “lab to fab\,” sharing practical insights on leadership\, resilience\, and how we build the diverse\, future-ready talent pipeline needed to sustain innovation. \nThe opportunity is clear: when we connect the physical and digital worlds at scale\, we don’t just optimise systems\, we redefine what’s possible. \nBiography \nCatherine is a pioneer of ultra-thin semiconductor circuitry on flexible substrates. Consistently at the cutting edge of technology\, she has over 20 years’ industrial experience in the flexible electronics field.\nCatherine is a Fellow of the Royal Academy of Engineering\, holds a PhD in organic electronics from the University of Cambridge\, and is co-creator of 18 inventions\, leading to 64 granted patents. \n\nDetailsSvetlana GrantStrategic Partnership Lead for Robotics\, Google DeepMind \n×Svetlana Grant\n\nPrior to her career in AI and robotics\, Svetlana worked on mobile innovation and Internet of Things. She ran an innovation team at Vodafone Business IoT Technology division\, and prior to that\, managed an IoT program at the GSMA and worked as a telecom industry analyst. After years of working in the telco industry\, she decided that AI was too fascinating to miss\, graduated with MSc in Integrated ML Systems from UCL and joined DeepMind in 2022. She is a reading addict\, a table tennis club organiser\, and a keen gardener. \n\nDetailsJanet Collyer MBEPortfolio Board Director and government advisor \n×Janet Collyer\nJanet is Chair of the Board at Quantum Dice\, Independent NED and Advisor at Mach42\, Independent NED at the Aerospace Technology Institute and also a member of the UK Government’s Semiconductor Advisory Panel and member of National Physics Laboratory’s Major Programme Portfolio Advisory Council.Prior to her portfolio career she held senior positions within the semiconductor industry most recently as Strategic Group Director at Cadence Designs System leading international teams\, driving bespoke approaches and effective ecosystem partnerships that delivered business revenue growth across the semiconductor supply chain. \nAfter her engineering degree at Girton College Cambridge University she worked in the USA and UK in semiconductor design through to manufactured product shipping in volume. She and her team taped out over 300 devices.\nShe then moved into roles in electronic design automation at Cadence which spanned technical application engineering\, product management\, project management\, global services\, IP and software sales director. Her final role was as International Group Director Strategic Accounts. \nIn the 2025 New Year’s honours list she was awarded an MBE for services to quantum hardware and cyber security.\nLater in 2025 she was awarded a Lifetime Achievement Award from Electronics Weekly Women Leaders in Electronics and was named in the top 5 of Computer Weekly’s most influential woman in UK technology. \nShe mentors STEM professionals from under represented groups as they progress through the ranks all the way to C-suite. \n\nSession HostsDetailsRas AttaleSenior Hardware Engineer\, Siemens \n×Ras Attale\nA Senior Hardware Engineer at Siemens\, with nearly seven years of experience on the team. Previously worked at Arm\, contributing to their verification team in Cortex A. Also currently pursuing a Master’s in Cybersecurity at the University of Oxford.\nDetailsDr Becky EllisSenior Manager Research Enablement\, Arm \n×Dr Becky Ellis\nDr Becky Ellis is a research enablement and programme leader with more than 20 years’ experience driving community growth\, stakeholder engagement and talent development across education and technology. At Arm\, she leads the global Arm Academic Access initiative that democratises access to semiconductor and SoC design technologies\, enabling universities worldwide to advance research\, education and innovation.\nPanellistsDetailsHelen LedgerSenior Vice President of Marketing\, Pragmatic Semiconductor \n×Helen Ledger\n\nPanel Moderator \nHelen Ledger is a global B2B marketing leader with over 20 years’ experience driving growth\, brand leadership and market creation spanning AI\, IoT and semiconductor technologies. \nCurrently\, Senior Vice President of Marketing at Pragmatic Semiconductor\, she leads the global corporate marketing function\, shaping the company’s brand\, communication and public affairs activities\, while building high-performing teams and scalable demand engines. \nPreviously\, Helen held senior marketing leadership roles at Qualcomm\, where she led marketing for IoT and Automotive\, and contributed to multi-billion-dollar growth initiatives through integrated marketing\, brand strategy and ecosystem partnerships. Prior roles span marketing leadership positions based in London at D-Link\, a Taiwanese networking manufacturer and British Telecom\, and Sophia-Antipolis\, France with France Telecom. \nHelen is passionate about inclusive leadership\, developing talent\, and aligning marketing as a true growth engine for business transformation \n\nDetailsCaroline O’BrienCEO\, CSA Catapult \n×Caroline O'Brien\n\nA semiconductor industry specialist\, Caroline O’Brien brings over 30 years of experience in the technology sector\, where she has developed a broad knowledge of working with VC-backed businesses and blue-chip multinationals. \nShe has held senior commercial and executive positions in several companies\, focusing on developing and commercialising new technologies and products. \nCaroline holds a B.Eng in Electronics and Electrical Engineering and an MBA from the University of Bath. \n\nDetailsFarah ComisCEO\, Altro Photonics \n×Farah Comis \n\nFarah Comis is the CEO of Altro Photonics.  She completed her PhD in the Optical Networks Group at University College London (UCL)\, supervised by Dr. Alfonso Ruocco. She holds an MEng in Electronic and Electrical Engineering from UCL and an MRes in Connected Electronic and Photonic Systems from the University of Cambridge. \nHer PhD thesis\, Integrated Photonic Platforms for Next-Generation Optical Transmitters\, focused on integrated photonics using high-index-contrast platforms including silicon nitride on insulator (SiNOI) and lithium niobate on insulator (LNOI). She developed state-of-the-art silicon and lithium-niobate modulators and quantum devices\, resulting in first-author publications in Optics Express and Optics Letters\, a patent filing\, and presentations at IEEE Silicon Photonics and CLEO\, as well as an invited talk at the CORNERSTONE User Day. \nAlongside her research\, Farah is spinning out technology from UCL into a spin-out. She is part of the Future Worlds accelerator and previously participated in the 50:50 program backed by 50 Years VC\, supporting the commercialisation of an integrated photonics platform. \n\nDetailsJen WallsCEO\, Clas-SiC \n×Jen Walls\n\nJen brings over 30 years Semiconductor Industry experience within operational and managerial positions in Equipment\, Process Engineering\, Process Development and Business Management. Jen has successfully led many SiC projects and was key in the early Silicon Carbide industry engagements in the UK. She is an Engineering and MBA graduate and is a certified 6-sigma green belt practitioner. Jen joined Clas-SiC as Chief Operations Officer\, stepping up to the CEO role from January 2024. Since moving into the role\, Clas-SiC has secured equity investment to secure the next part of their technology roadmap as the company continues to grow. \n\nDetailsKarima DridiHead of Productivity Engineering (CE-PE)\, Arm \n×Karima Dridi\n\nKarima Dridi is Head of Productivity Engineering at Arm\, where she is driving the transformation of engineering enablement through infrastructure\, tooling\, and AIpowered workflows. \nBefore leading PE\, Karima headed up Delivery and Engineering Enablement within Central Engineering Operations\, focusing on technical resources\, compliance\, and lifecycle management. With over 20 years in the semiconductor industry — including roles at Infineon\, Texas Instruments\, and Arm. \nKarima has built and led global teams across SoC design\, CPU delivery\, and strategic engineering initiatives. Karima is passionate about empowering engineers through scalable systems\, smart automation\, and a bold\, 10X mindset. \n\nDetailsJon MichaelsDirector\, microTECH \n×Jon Michaels\n\nJon Michaels is the Director and Co-founder of microTECH Global Ltd\, a talent solutions firm specialising in the Deep Tech sector with Divisions spanning Semiconductors\, Technology including AI\, Software & Hardware Electronics and Executive search. Jon co-founded microTECH Global in 2013 with the vision of delivering expert talent acquisition services to some of the most innovative and influential companies in the market. He graduated with an Electronics & Communications degree from Leeds Met and has over 20 years of recruitment experience within the Deep Tech industry. He remains hands-on to this day\, delivering exceptional talent to pre-seed\, seed-stage\, and established businesses\, with a deep understanding of each stage of growth and the scaling journey of a tech firm. \nUnder his leadership\, microTECH has grown into a multi-division\, multi-site organisation\, partnering with businesses of all sizes\, from early-stage start-ups to established global leaders. The company is recognised not only for sourcing high-impact talent\, on a permanent and consultancy basis\, but also for providing strategic hiring advice and supporting the development of long-term talent roadmaps. \nFrom building teams and launching new divisions to enabling complex talent transfers across Europe and beyond\, microTECH continues to be a trusted partner in driving growth and innovation across the tech landscape.
URL:https://techworks.org.uk/event/women-in-techworks-engineering-intelligently/
LOCATION:Arm\, 110 Fulbourn Rd\, Cambridge\, CB1 9NJ
CATEGORIES:past-events,TechWorks,Women in TechWorks
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260615T100000
DTEND;TZID=Europe/London:20260615T160000
DTSTAMP:20260527T103844Z
CREATED:20260527T103844Z
LAST-MODIFIED:20260527T103844Z
UID:7396-1781517600-1781539200@techworks.org.uk
SUMMARY:You're not ready for the CRA
DESCRIPTION:The EU Cyber Resilience Act (CRA) is set to fundamentally change how connected products are designed\, developed\, secured\, and maintained – yet many organisations are still underestimating the scale of the challenge.\nThis event brings together security leaders\, product teams\, compliance specialists\, and IoT innovators to discuss what the CRA actually means in practice\, where companies are falling behind\, and what needs to happen now to prepare. \nWe’ll explore the operational\, technical\, and organisational gaps that are preventing businesses from becoming CRA-ready\, including secure development practices\, vulnerability management\, SBOMs\, supply chain visibility\, post-market obligations\, and product accountability. \nWhether you’re building connected devices\, managing product security\, navigating compliance requirements\, or advising organisations on cyber risk\, this event is designed to spark honest conversations about the current state of readiness across the industry. \nTopics and speakers will be announced soon. \nWho should attend: \n– IoT and product security professionals\n– CISOs and security leaders\n– Compliance and regulatory teams\n– Product and engineering leaders\n– Device manufacturers and OEMs\n– Cybersecurity consultants and researchers \nJoin us for an open discussion on the future of IoT security – and why the industry needs to move faster.
URL:https://techworks.org.uk/event/youre-not-ready-for-the-cra/
LOCATION:PA Consulting\, 7th floor\, 10 Bressenden Place\, London\, SW1E 5DN
CATEGORIES:IoTSF,past-events,TechWorks
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260614
DTEND;VALUE=DATE:20260618
DTSTAMP:20260428T170531Z
CREATED:20260428T170300Z
LAST-MODIFIED:20260428T170531Z
UID:6757-1781395200-1781740799@techworks.org.uk
SUMMARY:29th World Micromachining Summit
DESCRIPTION:
URL:https://mms2026.soton.ac.uk/#new_tab
LOCATION:Southampton
CATEGORIES:DESN,NMI,past-events,Promoted,TechWorks
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/04/NEW-TechWorks-site-images-9.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260520T140000
DTEND;TZID=Europe/London:20260520T150000
DTSTAMP:20260511T134751Z
CREATED:20260511T134539Z
LAST-MODIFIED:20260511T134751Z
UID:7013-1779285600-1779289200@techworks.org.uk
SUMMARY:"Female Business Leaders and Founders: Challenges and Opportunities for Growth" at Innovation Fest
DESCRIPTION:📅 Wednesday 20 May 2026\n🕑 2:00–3:00pm\n📍 CST 008\, STEAMhouse (Main Stage) \nThis session brings together a carefully selected group of female founders and business leaders to explore the realities of building and scaling ventures\, sharing practical insights on growth\, leadership\, and opportunities within the current landscape. The session will be delivered as a moderated panel discussion followed by audience Q&A. \nWe’re expecting an engaged audience of founders\, professionals\, and individuals across the innovation and business ecosystem\, and it would be great if you were able to share this with your team and wider network. \nThe wider Innovation Fest programme is available on the website. Guests can register via the website by selecting Wednesday and noting the panel “Female Founders Panel” in the comments:
URL:https://techworks.org.uk/event/female-business-leaders-and-founders-challenges-and-opportunities-for-growth-at-innovation-fest/
LOCATION:University of Birmingham\, Birmingham City University\, Curzon Building 4 Cardigan Street\, Birmingham\, B4 7BD
CATEGORIES:past-events,TechWorks
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260519
DTEND;VALUE=DATE:20260520
DTSTAMP:20260511T140331Z
CREATED:20260511T140331Z
LAST-MODIFIED:20260511T140331Z
UID:7017-1779148800-1779235199@techworks.org.uk
SUMMARY:Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs
DESCRIPTION:
URL:https://www.synopsys.com/webinars/intel-3d-multi-die-design-signoff.html?utm_source=techworks&utm_medium=link&utm_campaign=mds&utm_content=intel-signoff-wbnr_link_mul_wbn&tags=Webinars#new_tab
CATEGORIES:Member Event,past-events
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/05/square-1000px-image-72.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260514T120000
DTEND;TZID=Europe/London:20260514T123000
DTSTAMP:20260305T110250Z
CREATED:20260305T110250Z
LAST-MODIFIED:20260305T110250Z
UID:5891-1778760000-1778761800@techworks.org.uk
SUMMARY:AESIN Webinar: ADAS Fit for the Future
DESCRIPTION:New Advanced Driver Assistance Systems (ADAS) are transforming the way we interact with our car and shaping the road towards full autonomy. \n\nWhere is the technology today?\nWhat are the emerging features?\n\nSuch as predictive safety\, driven by legislation changes.\n\n\nWhat are the leading ADAS features for various OEMs/vehicles?\n\nWhat is the plan for the future?\nAnd the challenges with implementing these?\n\n\n\nYou will gain insights into the innovations on the horizon and the regulatory forces accelerating or constraining progress in this exciting and rapidly evolving domain.
URL:https://techworks.org.uk/event/aesin-webinar-adas-fit-for-the-future/
LOCATION:Webinar
CATEGORIES:AESIN,past-events,TechWorks
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260512T080000
DTEND;TZID=Europe/London:20260512T170000
DTSTAMP:20260429T110606Z
CREATED:20260429T110507Z
LAST-MODIFIED:20260429T110606Z
UID:6769-1778572800-1778605200@techworks.org.uk
SUMMARY:Intel: Enabling and Evaluating Intel EMIB-T Bridging Design with Synopsys Tools
DESCRIPTION:
URL:https://www.synopsys.com/webinars/intel-emib-t-design-advanced-ai-datacenter-solutions.html?utm_source=techworks&utm_medium=link&utm_campaign=mds&utm_content=intel-emib-t-wbnr_link_mul_wbn&tags=Webinars#new_tab
CATEGORIES:Member Event,past-events,Webinar
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/04/NEW-Techworks-site-featured-images-2026-04-29T115957.084.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260430
DTEND;VALUE=DATE:20260501
DTSTAMP:20260410T152849Z
CREATED:20260408T100947Z
LAST-MODIFIED:20260410T152849Z
UID:6357-1777507200-1777593599@techworks.org.uk
SUMMARY:Synopsys: Powering 3D Multi-Die Designs with RedHawk-SC Electrothermal
DESCRIPTION:
URL:https://www.synopsys.com/webinars/powering-3dic-systems-redhawk-sc-electrothermal.html?utm_source=techworks&utm_medium=link&utm_campaign=mds&utm_content=redhawk-sc-for-multi-die-designs_link_mul_wbn&tags=Webinars#new_tab
CATEGORIES:Member Event,past-events,Promoted
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260430
DTEND;VALUE=DATE:20260501
DTSTAMP:20260410T153442Z
CREATED:20260410T151856Z
LAST-MODIFIED:20260410T153442Z
UID:6384-1777507200-1777593599@techworks.org.uk
SUMMARY:Marvell: Accelerating Interposer Design with Early Signal Integrity Analysis
DESCRIPTION:In this webinar\, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early\, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated\, compute intensive 3D FEM cycles during development\, Marvell uses a Method of Moments (MoM) early SI check available within Synopsys 3DIC Compiler to evaluate routing with real parasitics and simulation data\, fast enough to support rapid iteration and safer exploration of auto routing strategies. Marvell will also share practical correlation takeaways\, where MoM tracks FEM strongly and where additional margin and correlation work may be needed ahead of final signoff.
URL:https://techworks.org.uk/event/marvell-accelerating-interposer-design-with-early-signal-integrity-analysis/
CATEGORIES:Member Event,past-events,Promoted
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/04/NEW-Techworks-site-featured-images-2026-04-10T161735.559.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260429
DTEND;VALUE=DATE:20260430
DTSTAMP:20260413T090240Z
CREATED:20260413T090240Z
LAST-MODIFIED:20260413T090240Z
UID:6389-1777420800-1777507199@techworks.org.uk
SUMMARY:Application-Specific Processors (ASIPs) for Physical AI
DESCRIPTION:
URL:https://www.synopsys.com/webinars/application-specific-processors-asip-physical-ai.html?utm_source=techworks&utm_medium=link&utm_campaign=sip_processor-ip&utm_content=asips-pysical-ai-wbnr_link_mul_wbn&tags=Webinars#new_tab
CATEGORIES:Member Event,past-events,Promoted
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/04/NEW-Techworks-site-featured-images-2026-04-13T095807.869.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260423T160000
DTEND;TZID=Europe/London:20260423T163000
DTSTAMP:20260612T121430Z
CREATED:20260302T111641Z
LAST-MODIFIED:20260612T121430Z
UID:5828-1776960000-1776961800@techworks.org.uk
SUMMARY:How to move from Individual Contributor to Leader in a Male Dominated Environment: A Women in TechWorks Fireside Chat
DESCRIPTION:Our speaker will be talking from two perspectives – firstly her own experience moving into leadership\, and secondly as a leader what I look for in high potential juniors and the behaviours that are helpful \nBiography \nEllie Bramer is an Engineering Manager at Arm\, where she leads multiple teams of software engineers at the intersection of advanced computing\, AI\, and ecosystem innovation. With a background as a systems engineer in the defence sector she has built her career in male-dominated environments\, progressing from individual contributor to experienced engineering leader. Ellie is passionate about building high-performing technical teams and creating pathways for more women to thrive and advance in engineering and tech fields.
URL:https://techworks.org.uk/event/how-to-move-from-individual-contributor-to-leader-in-a-male-dominated-environment-a-women-in-techworks-fireside-chat/
LOCATION:Webinar
CATEGORIES:past-events,TechWorks,WITW-Past Event,Women in TechWorks
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260423T140000
DTEND;TZID=Europe/London:20260423T150000
DTSTAMP:20260410T152118Z
CREATED:20260326T114231Z
LAST-MODIFIED:20260410T152118Z
UID:6249-1776952800-1776956400@techworks.org.uk
SUMMARY:IoTSF Webinar: CRA Reporting Obligations with Mustanir Ali (Element)
DESCRIPTION:
URL:https://us06web.zoom.us/webinar/register/WN_Lg_DkdFZSx-6TwSdFY5Hxg#/registration#new_tab
CATEGORIES:IoTSF,past-events,TechWorks,Webinar
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260416
DTEND;VALUE=DATE:20260417
DTSTAMP:20260413T174423Z
CREATED:20260123T154352Z
LAST-MODIFIED:20260413T174423Z
UID:4805-1776297600-1776383999@techworks.org.uk
SUMMARY:FPGA Frontrunners @ Microchip
DESCRIPTION:CLICK HERE to find out more about the FPGA Frontunners group \n\nField Programmable Gate Arrays (FPGAs) play a critical role in modern electronic systems\, powering applications that range from everyday consumer products to mission-critical infrastructure. Their ability to be customized and reconfigured after deployment makes them uniquely valuable in fast-moving technology environments. At the same time\, this adaptability introduces distinct security challenges that must be carefully addressed. \nBecause FPGAs can be reprogrammed in the field\, they present a broader attack surface than fixed-function hardware. Threats targeting configuration data\, intellectual property\, firmware integrity\, and runtime behavior can compromise not only the device itself\, but also the larger systems that rely on it. As FPGAs are increasingly used to support advanced workloads—including data-intensive and intelligent processing—security risks continue to grow in both scope and impact. \nEffective FPGA security extends beyond physical protection. It encompasses the full lifecycle and ecosystem surrounding the device\, including design tools\, bitstreams\, firmware\, software interfaces\, and data flows. In systems that incorporate adaptive or AI-assisted functionality\, ensuring trust\, integrity\, and resilience across this ecosystem is especially critical. \nThis event explores the evolving landscape of FPGA security\, highlighting emerging threats\, recent advances\, and proven mitigation strategies. Through expert insights and real-world case studies\, the program aims to equip engineers\, researchers\, and security professionals with practical guidance for securing FPGA-based systems today and in \nknowledge\, techniques\, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so. \nWho Should Attend\n\nFPGA Designers and Engineers\nSystem Architects\nSafety and Security Specialists\nSupply Chain Professionals\nIndustry Regulators and Standards Bodies\n\nWhy Attend? \n\nGain insights from leading experts on the evolving risks and mitigation strategies\nLearn how to meet functional safety and security requirements across multiple industries\nNetwork with industry peers and potential collaborators\nParticipate in discussions on best practices\, regulatory trends\, and real-world case studies\n\nAgenda\n\n\n\n\nTime\nDetails\n\n\n\n\n10:00\nRegistration\n\n\n10:30\nMicrochip Secure FPGA’s\nIan Pearson\nPr. ESE\, Microchip\n\n\n11:00\nA Visual Demonstration of True Random Numbers from a Quantum Computer\nPhill J Payne\nPrincipal Digital Design Engineer\, Novomorphic\n\n\n11:30\nAre FPGAs unique for security?\nMartin Thompson\nSenior Technical Specialist\, ZF Engineering Solutions\n\n\n12:00\nBeyond Bitstream Encryption: FPGA Security for High-Assurance Systems\nDaniel Tee\nSenior Firmware (FPGA) Engineer\, Leonardo\n\n\n12:30\nNetworking Lunch\n\n\n13:30\nOverview of prEN50767 : CRA Vertical Standard for FPGA/ASIC\nPeter Trott\nStaff FAE\, Microchip\n\n\n14:00\nHardware-Rooted Bitstream Security\nMans Ahmadian\nChief Innovation Officer\, Sundance\n\n\n14:30\nWrap Up\n\n\n14:45\nClose\n\n\n\n\nSpeakersDetailsPhill J Payne \nPrincipal Digital Design Engineer\, Novomorphic \n×Philip Payne\nPrincipal Digital Design Engineer\, Novomorphic\nPresentation: A Visual Demonstration of True Random Numbers from a Quantum Computer \nTrue randomness is one of those things everyone assumes they have… right up until security\, trust\, or assurance actually matters.\nThis session reveals a practical way to pull physical entropy from a real quantum computer and inject it into FPGA and embedded systems as a usable\, engineering-grade input. You’ll see quantum behaviour turned into something tangible and immediate — a live “quantum dice” demonstrator that makes the invisible visible — and you’ll learn why this matters far beyond novelty. \nWe’ll explore what changes when your randomness isn’t “noisy enough” pseudo-random\, but rooted in genuine physical uncertainty\, and how that can reshape thinking around key generation\, nonces\, reseeding\, and trusted system design. A live comparison between simulation and real quantum hardware draws a clear line between “looks random” and “is random”. \nIf you build secure edge systems and care about trust boundaries\, this will change how you think about entropy. \nBiography \nPhill J Payne is Principal Digital Design Engineer at Novomorphic\, specialising in secure\, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines\, reduces memory pressure\, and delivers high-performance vision and inference at the edge. Across 26 years\, Phill has turned novel architectural ideas into deployable systems under tight power\, latency\, throughput\, and reliability constraints\, with deep experience in security-grade FPGA development and signal-processing workloads. Previously\, he delivered end-to-end FPGA firmware and software for advanced systems\, including a patented communications technique designed to operate in contested jamming environments\, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games\, translating complex engineering into practical tools. \nCloseDetailsMartin Thompson \nSenior Technical Specialist\, ZF Engineering Solutions \n×Martin Thompson\nSenior Technical Specialist\, ZF Engineering Solutions\nPresentation: Are FPGAs unique for security? \nIn this talk we will investigate the degree to which systems containing programmable logic (including FPGAs) can be considered “unique” in their security requirements and implementation options\, when compared to more conventional microcontroller and desktop processor systems. \nWe will briefly define what we mean by “security” in this context (both in terms of market requirements and attacker motivations) and what primitives can be used to achieve it. A review of the variety of potential attacks will be presented and we will spend some time on the peculiarities of FPGA-based systems by comparing them directly with other implementation strategies. Finally\, we will conclude with an answer to the question posed in the title. \nBiography \nMartin Thompson is a Senior Technical Specialist at ZF Engineering Solutions. He has spent over 30 years developing systems and algorithms for products in the automotive and aerospace domains. He enjoys working across the full range of software and electronics disciplines\, from desktop algorithm development to microcontroller\, DSP and FPGA code as well as electronic design\, PCB layout (and when the need arises\, soldering!). He specialises in optimisations of whole electronic systems\, based on a detailed understanding of the trade-offs across multiple domains. Particular highlights have included the development of very low-cost FPGA-based imaging and radar-systems. \nSince 2015\, Martin has been heavily involved in the cybersecurity of embedded systems and is currently the technical leader of an penetration-testing team with an embedded-system focus. He contributes to the Internet of Things Security Foundation Assurance Framework\, the Automotive Threat Matrix\, and is a member of the MITRE hardware CWE SIG and the CWE-RTL working group. Finally\, he spends some of his time researching novel side-channel attacks in pursuit of a PhD\, with the University of Durham. \nCloseDetailsIan Pearson \nPr. ESE\, Microchip Technology Inc. \n×Ian Pearson\nPr. ESE\, Microchip Technology Inc.\nPresentation: Leveraging Microchip Secure FPGAs \nThe foundation of a secure end product lies in the right choice of components. CRA requires a ‘Secure by Design’ approach to product development and support throughout the lifecycle. Microchip FPGA’s have a long history of secure FPGA’s designed to meet the most demanding of military applications but available to all \nBiography \nIan Pearson is a Principle Embedded Solutions Engineer with Microchip Technology covering FPGA\, Security and IoT. He is also the chair of the IoT Security Foundation – Security Assurance Framework Working Group.CloseDetailsMans Ahmadian \nChief Innovation Officer\, Sundance \n×Mans Ahmadian\nChief Innovation Officer\, Sundance\nPresentation: Hardware-Rooted Bitstream Security and Secure Manufacturing Workflow \nA Defense-Grade Implementation Using PolarFire FPGA on Sundance PCIe104N Platform As FPGAs become central to mission-critical defense and aerospace systems\, the security challenge has shifted. It is no longer enough to protect configuration data in the fi eld; we must also secure it during manufacturing\, programming\, testing\, and across the entire supply chain. When production is distributed across multiple facilities and third-party partners\, the FPGA bitstream becomes a high-value target\, vulnerable to interception\, overbuilding\, hardware substitution\, or reverse engineering. This talk presents a defence-grade secure provisioning workflow implemented on the Sundance PCIe104N platform\, built around the PolarFire MPF500T FPGA\, and explains how it establishes trust from silicon to system deployment. \nAt the heart of this approach is hardware-rooted security. PolarFire devices generate a unique\, silicon-derived identity using Physically Unclonable Functions (PUFs)\, meaning that no two FPGAs are electrically identical and no identity can be copied or cloned. During secure provisioning\, this identity is validated before any sensitive key material is transferred. The customer’s encrypted bitstream and User Encryption Key are generated inside their own trusted environment and securely delivered for programming using Microchip’s Secure Production Programming Solution. If authentication fails at any stage\, such as in a dummy FPGA impersonation attempt\, the process stops immediately. No keys are exposed\, and no firmware is released. What this workflow ultimately provides is confidence. Confidence that the hardware being programmed is genuine. Confidence that only the approved number of boards can ever be provisioned. Confidence that the bitstream cannot be intercepted\, modified\, or extracted through side-channel attacks. By combining controlled manufacturing\, independent validation\, hardware security modules\, authenticated encryption\, and built-in DPA countermeasures\, Sundance ensures customers receive fully tested\, securely programmed boards\, without any risk of supply-chain compromise or intellectual property leakage. Today\, I will walk you through how this architecture works and why it sets a scalable model for secure FPGA manufacturing. \nBiography \nMans Ahmadian serves as the Chief Innovation Officer at Sundance\, where he leads the architecture of next-generation\, high-density AI Systems-on-Modules (SoMs). In this role\, he directs the design of specialized AI Engines and systems otimized for low-power\, high-throughput inference in rugged environments. He is instrumental in bridging the gap between AI frameworks and SundanceDSP hardware. Additionally\, his work ensures the reliability of autonomous Edge AI platforms in mission-critical settings by optimizing SWaP (Size\, Weight\, and Power) solutions and integrating safety-critical\, “fail-safe” R&D workflows. \nThroughout his career\, he has been granted numerous patents for his innovations in image processing\, advanced camera systems and imaging sensor operations. His technical and commercial achievements have earned him several prestigious honors\, including the IET (Institute of Engineering and Technology) Innovation Award in software development\, the SMART::SCOTLAND Innovation Award\, and a Business Plan Competition win. These accolades are supported by a robust academic foundation\, including a PhD in Medical Image Processing\, an MSc in Biomedical/Medical Engineering\, and a BSc in Electronics from The University of Edinburgh\, and postgraduate certificates in Health Data Science and Big Data and AI. \nCloseDetailsPeter Trott \nStaff FAE\, Microchip Technology Inc. \n×Peter Trott\nStaff FAE\, Microchip Technology Inc.\nPresentation: Overview of prEN50767 : CRA Vertical Standard for FPGA/ASIC \nThe EU CRA requirements can be met via a presumption of conformity using horizontal and vertical harmonised standards. These standards are in development and will release very close to the enforcement date. In this session we will give some insight into what is coming in the vertical standard for FPGA/ASIC. The prEN50767 standard provides the requirements for FPGA/ASIC vendors to meet the Important Class I categorisation of FPGA/ASIC in the EU CRA. \nBiography \nPeter Trott is a Staff Applications engineer at Microchip with over 30yrs experience in the FPGA sector. He has extensive experience in both military and industrial design using FPGA’s. Peter is also a key member of the EU TC47x WG4 Trusted Silicon work group for FPGA/ASIC who are creating the prEN50767 harmonised standard relative to the Important Class I FPGA/ASIC with security features \nCloseDetailsDaniel Tee \nSenior Firmware (FPGA) Engineer\, Leonardo. \n×Daniel Tee\nSenior Firmware (FPGA) Engineer\, Leonardo.\nPresentation: Beyond Bitstream Encryption: FPGA Security for High-Assurance Systems \nField programmable gate arrays (FPGAs) are increasingly deployed in systems where failure or compromise is not an option – from defence and aerospace to critical infrastructure and advanced industrial platforms. In these high assurance environments\, security requirements extend beyond the protections normally offered by device vendors. Engineers must consider the broader context of threats\, deployment conditions\, and system level risk. \nBiography \nDaniel Tee is a Senior Firmware (FPGA) Engineer at Leonardo\, working within the product security team. He joined Leonardo as a graduate in 2022 after completing an integrated MEng in Electronics and Computer Science at the University of Edinburgh\, where he focused on a number of cybersecurity modules in his final year. Daniel now applies his interest in hardware security to developing robust FPGA‑based security solutions for customer‑driven\, mission‑critical applications. \nClose
URL:https://techworks.org.uk/event/fpga-frontrunner-microchip/
LOCATION:Microchip\, 720 Wharfedale Rd\, Winnersh\, Wokingham\, RG41 5TP
CATEGORIES:DESN,past-events,TechWorks
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260331T091500
DTEND;TZID=Europe/London:20260331T172000
DTSTAMP:20260331T091916Z
CREATED:20260116T172352Z
LAST-MODIFIED:20260331T091916Z
UID:4700-1774948500-1774977600@techworks.org.uk
SUMMARY:Designing the Future: Analogue Mixed Signal (AMS)
DESCRIPTION:As complexity accelerates\, designers face growing challenges in architecture\, design\, system scaling and workflow.\nFollowing our first event on Digital SoC Design in November\, this hands-on event brings together Analogue and Mixed Signal chip architects and designers to explore real-world pain points and application trends\, sharing lessons learned. During this event\, we will explore the key challenges and opportunities facing industry and identify potential collaboration to support industry growth. \nWe will explore three contemporary themes during the event\, with a plenary discussion following each one to discuss the topics raised and identify relevant actions going forward. \nRunning concurrently at the same venue\, TechWorks and UKESF are hosting a Chip Design Early Careers event which will bring together industry and emerging talent. The UKESF Digital Design – Early Careers track\, will give companies the opportunity to engage with up to 50 students and graduates: next-generation chip designers at the point where they are actively making career choices. Participants can speak directly to students and early-career engineers who want to learn more about chip design as a career\, and which organisations they can join and grow with. \nThe future of AMS Design \nHow is AMS design evolving and where are we compared with pure-play digital CMOS\nPotential themes: \n\nDesign for performance\, noise\, and integrity across PVT\nTrade-offs across process nodes and analogue scaling limits vs digital scaling; voltage range\, noise\, performance\, cost\nDesign migration\, IP integration and reuse\nDesign flow and productivity: How can automation and AI help?\nLayout challenges\, routing\, optimization and physical verification\nCo-simulation\, model abstraction and system-level verification\n\nSystem architecture and Integration \nMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration? \nPotential themes: \n\nSystem partitioning\, simulation and integration: Performance / Power / Area\nDigital-analogue interfacing and interconnect. Interference mitigation and isolation\nMulti-die integration: Yield reliability\, Power delivery\, Thermal management\nSignal integrity and noise coupling in advanced packaging\, 2.5D and 3D\nMulti-die mixed signal chiplets and heterogeneous integration\n\nApplication drivers for AMS Design \nMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today? \nPotential themes: \nFuture compute (AI\, Data centres\, High-performance compute) \n\n\n\nHigh-speed SerDes\, Photonic interconnect and Clock and Data Recovery\nPower delivery networks\, voltage regulation\, and monitoring\nAnalog and in-memory compute\n\n\n\nIoT\, connectivity\, med-tech and wearables \n\n\n\nLow-noise analogue sensor front ends\nEdge AI / Neuromorphic compute\nSensor – Edge AI integration\nLow power RF\nEnergy harvesting\nSecurity\n\n\n\n\n×Meet the students\n\nFrom RTL and verification to open-source silicon tapeouts\, these exceptional students are already making an impact in digital chip design \n James Ashie Kotey | Electronics & Computer Engineering\, University of Sheffield | IC Engineering Intern at EnSilica \nJames has contributed to commercial ASIC projects in RTL design and functional verification\, and has led three open-source silicon projects from concept to tapeout using open-source EDA tools and PDKs. \nCarys MacIntyre | Robotics Engineering (Integrated Master’s)\, University of Bath | Hardware Intern at Siemens EDA (Tessent Embedded Analytics) \nCurrently on a 12-month placement in digital RTL verification\, Carys is gaining hands-on verification experience alongside her master’s studies. \nCharlie Teare | Mechatronics & Robotic Systems (BEng with Year in Industry) \, University of Liverpool \nFollowing a placement with EnSilica’s digital design team\, Charlie continues collaborating with industry while completing his final year project focused on a fabric/interconnect generator. \nRonit Ravi | Electronic Engineering\, Imperial College London \nNow in his final year\, Ronit previously completed a placement in Design Verification at Siemens EDA and continues to collaborate during his master’s research. \nThis event provides students and early-career designers with direct exposure to professionals in digital chip design \,  embedding their learning and offering tangible inspiration for careers in the UK semiconductor sector. \n\n\n  \n\n\n\nTIME\nDETAILS\n\n\n\n\n09:15\nRegistration\n\n\n10:00\nTechWorks DESN Introduction – Scene setting & objectivesJillian Hughes\, Head of Semiconductors\, DESN & Charles Sturman\, CEO\, TechWorks\n\n\n \nThe Future of AMS DesignHow is AMS design evolving and where are we compared with pure-play digital CMOS\n\n\n10:10\nSystem-First Design for High-Performance Mixed-SignalAsad Ali\, Senior IC Architect\, Novamorphic\n\n\n10:30\nBridging the Verification Gap Between Digital and Analog IC Design Marcel Ahmedzai\, Application Engineer Architect\, Cadence\n\n\n10:50\nTop‑Down Approach to Mixed‑Signal VerificationGautham Sathyan\, Mixed Signal Modeling & Verification Engineer\, Cirrus Logic\n\n\n11:10\nVerifying AMS DesignsMike Bartley\, CEO\, Alpinum\n\n\n11:30\nDiscussion and CTA\n\n\n11:55\nSponsor talk: Lee Harrison\, Director of Product Marketing\, Tessent\, Siemens EDA\n\n\n12:00\nNetworking Lunch\n\n\n \nSystem architecture and IntegrationMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?\n\n\n13:00\nStructured AMS migration: Device-level validation to layout closure with intelligent automationChris Yates\, Head of AI and Machine Learning\, Thalia\n\n\n13:20\nRevolutionizing Analog Layout Synthesis through GenAI and Machine Learning TechnologiesNeel Goplan\, Executive Director\, Technical Product Management\n\n\n13:40\nBeyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/OsBart Keppens\, Chief Business Development\, Sofics\n\n\n14:00\nDiscussion & Call to Action\n\n\n14:25\nBreak\n\n\n \nApplication drivers for AMS DesignMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?\n\n\n15:10\nAMS from beamforming arrays to safety critical ASICsKonstantinos Glaros\, Associate Director – Analogue IC Design\, Ensilica Plc\n\n\n15:20\nAnalog Scan: A new frontier for Mixed-signal testVladimir Zivkovic\, Principal Product Engineer\, Siemens EDA\n\n\n15:40\nDiscussion & Call to Action\n\n\n16:05\nRefreshments and Networking\n\n\n17:00\nClose\n\n\n\n\nAgenda\n\n\n\n\n09:15Registration\n\n\n10:00TechWorks DESN Introduction – Scene setting & objectivesJillian Hughes\, Head of Semiconductors\, DESN & Charles Sturman\, CEO\, TechWorks\n\n\nThe Future of AMS DesignHow is AMS design evolving and where are we compared with pure-play digital CMOS\n\n\n10:10System-First Design for High-Performance Mixed-SignalAsad Ali\, Senior IC Architect\, Novamorphic\n\n\n10:30Bridging the Verification Gap Between Digital and Analog IC DesignMarcel Ahmedzai\, Application Engineer Architect\, Cadence\n\n\n10:50Top‑Down Approach to Mixed‑Signal VerificationGautham Sathyan\, Mixed Signal Modeling & Verification Engineer\, Cirrus Logic\n\n\n11:10Verifying AMS DesignsMike Bartley\, CEO\, Alpinum\n\n\n11:30Discussion and CTA\n\n\n11:55Sponsor talk: Lee Harrison\, Director of Product Marketing\, Tessent\, Siemens EDA\n\n\n12:00Networking Lunch\n\n\nSystem architecture and IntegrationMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?\n\n\n13:00Structured AMS migration: Device-level validation to layout closure with intelligent automationChris Yates\, Head of AI and Machine Learning\, Thalia\n\n\n13:20Revolutionizing Analog Layout Synthesis through GenAI and Machine Learning TechnologiesNeel Goplan\, Executive Director\, Technical Product Management\n\n\n13:40Beyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/OsBart Keppens\, Chief Business Development\, Sofics\n\n\n14:00Discussion & Call to Action\n\n\n14:25Break\n\n\nApplication drivers for AMS DesignMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?\n\n\n15:00AMS from beamforming arrays to safety critical ASICsKonstantinos Glaros\, Associate Director – Analogue IC Design\, Ensilica Plc\n\n\n15:20Analog Scan: A new frontier for Mixed-signal testVladimir Zivkovic\, Principal Product Engineer\, Siemens EDA\n\n\n15:40Discussion & Call to Action\n\n\n16:05Refreshments and Networking\n\n\n17:00Close\n\n\n\n\nAMS SpeakersDetailsChris Yates \nHead of AI and Machine Learning\, Thalia \n×Chris Yates\nHead of AI and Machine Learning\, Thalia\nStructured AMS migration: Device-level validation to layout closure with intelligent automation  \nAnalog and mixed signal IP migration using manual or in-house methods is rarely optimal and often slow and difficult. Y et migration remains necessary due to commercial and technical pressures. This session outlines practical ways to make migration predictable and efficient\, including automated device-level comparison\, early PPA assessment and intelligent layout adaptation. Drawing on recent project experience with machine learning-enhanced tools\, it demonstrates how AMS engineers can preserve performance while establishing a repeatable migration methodology. The approach combines traditional analog expertise with selective automation to reduce iteration cycles and improve reliability. The discussion will show where intelligent tools can augment\, not replace\, engineering judgment in critical design decisions. \nBiography \nChris Yates\, Vice President of Software Engineering\, leads development of EDA software for analog and mixed-signal design\, optimisation and technology migration. His work applies statistical methods\, mathematical optimisation and AI and machine learning to automate performance tuning and preserve circuit intent across process nodes. With a background in statistics\, mathematics and artificial intelligence\, he focuses on reducing design iteration time while maintaining predictability and robustness in advanced AMS flows. \nCloseDetailsMike Bartley \nFounder and CEO\, Alpinum \n×Mike Bartley\nFounder and CEO\, Alpinum\nVerifying AMS Designs \nWe will be investigating strategies for verifying AMS designs from test planning\, through test bench design and bring up\, to test generation\, closure and signoff. The talk will focus on practical\, best-practice verification solutions for a variety of designs\, so that the delegates can take away ideas that they can start using immediately. \nBiography \nMike started in software testing in 1988 after completing a PhD in Math\, moving to semiconductor Design Verification (DV) in 1994\, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones\, automotive\, comms\, cloud/data servers\, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies\, specialising in CPU verification. \nMike founded and grew a DV services company to 450+ engineers globally\, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP. \nMike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions. \nDetailsMarcel Ahmedzai \nApplication Engineer Architect\, Cadence \n×Marcel Ahmedzai\nApplication Engineer Architect\, Cadence\nBridging the Verification Gap Between Digital and Analog IC Design \nAs transistor geometries continue to shrink\, modern integrated circuit designs face escalating complexity that challenges the effectiveness and efficiency of traditional verification practices. Even at the block level\, the functional checks required to ensure correct behavior demand substantial time and resources\, and this burden increases dramatically when scaling to chip‑level and system‑level verification. In digital design\, these challenges have long been addressed through established verification methodologies\, dedicated verification engineers\, and standardized frameworks such as UVM. In contrast\, analog and mixed‑signal (AMS) design teams often lack a comparable verification mindset\, leading to late discovery of bugs\, costly respins\, and delays in time‑to‑market. This paper outlines the requirements and methodologies needed to elevate AMS verification to the maturity of its digital counterpart. By examining current gaps\, resource impacts\, and emerging best practices\, we provide a structured view of how systematic AMS verification can significantly reduce design risk and improve overall product quality. \nBiography \nMarcel Ahmedzai is an engineering architect at Cadence with a focus on mixed signal verification and is based in Bracknell\, England. Prior to Cadence he was a CAD engineer at Mitel Semiconductor and Zarlink Semiconductor. Marcel has been with Cadence for over 20 years and has a bachelor’s degree in Mathematics from the University of Hertfordshire. \nDetailsAsad Ali \nSenior IC Architect ‑ Analogue and Mixed Signal\,\nNovomorphic \n×Asad Ali\nSenior IC Architect ‑ Analogue and Mixed Signal\, Novomorphic\nSystem-First Design for High-Performance Mixed-Signal \nIn modern mixed-signal systems\, the analog figure-of-merit (FOM)\, capturing the signal-to-noise ratio (SNR) delivered per unit power over a defined bandwidth\, is a key determinant of overall system efficiency. As CMOS technology continues to scale\, reduced intrinsic gain\, lower supply voltages\, and increased variability are fundamentally limiting the ability of traditional analog design techniques to sustain competitive FOM\, directly impacting power budgets\, performance headroom\, and implementation cost. \nThis talk reframes the problem from a circuit-centric challenge to a system-level opportunity – a System First Approach. Rather than relying solely on device-level optimisation\, we examine architectural and system-partitioning strategies that shift performance dependencies. \nWe present practical\, system-driven design methodologies that mitigate technology-imposed analog limitations\, enabling next-generation mixed-signal platforms to achieve aggressive performance targets while improving power efficiency\, scalability\, and time-to-market in line with Power-Performance-Cost objectives. \nBiography \nAsad Ali\, Senior IC Architect at Novomorphic\, champions a System First approach to analogue and mixed-signal development. He has held leadership roles at Maxim Integrated\, OnSemi\, Dialog Semiconductor and LSI Logic\, leading the development of high-volume RFIC\, power and mixed-signal IC products from concept to production.DetailsKostas Glaros \nAssociate Director – Analogue IC Design\, Ensilica Plc \n×Kostas Glaros\nAssociate Director – Analogue IC Design\, Ensilica Plc\nAMS from beamforming arrays to safety critical ASICs \nIn large\, multi-channel SoCs\, AMS verification is essential for validating the integration of multiple analogue channels operating concurrently alongside complex digital signal processing. Safety-critical ASICs\, such as industrial and automotive controllers\, demand demonstrable vertical integration and traceable compliance with requirements. This talk discusses examples of AMS and DMS verification in such applications and some associated challenges. \nBiography \nKostas Glaros is an analogue/mixed-signal technical lead with EnSilica Plc. Over the past decade he has led teams bringing multiple mixed-signal ASICs from initial concept to mass production. He focuses on medical\, automotive\, and industrial control applications\, and has a keen interest on design methodology and tools. Kostas holds a PhD in low-power medical electronics from Imperial College London. \nDetailsGautham Sathyan \nMixed Signal Modeling & Verification Engineer\, Cirrus Logic \n×Gautham Sathyan\nMixed Signal Modeling & Verification Engineer\, Cirrus Logic\nBiography \nGautham Sathyan is part of the Mixed-Signal Modeling and Verification group at Cirrus Logic in the Newbury office. His work spans a wide range of responsibilities\, including early stage architectural modeling of mixed signal blocks\, requirements definition\, and establishing analog/digital boundary and the chip level schematic hierarchy. He is involved in netlisting and chip bring up DMS simulation\, SystemVerilog real number modeling of low level analog cells\, and to define and implement chip level AMS simulations. \nWith a background in analog design\, Gautham particularly enjoys the challenges of modeling and debugging complex mixed signal systems. Outside of work\, he spends most of his time running after his young children\, though he hopes to one day start learning to play Indian music on the guitar. \nDetailsVladimir Zivkovic \nPrincipal Product Engineer\, Siemens EDA \n×Vladimir Zivkovic\nPrincipal Product Engineer\, Siemens EDA\nAnalog Scan: A new frontier for Mixed-signal test \nDeveloping tests for designs with mixed-signal circuits has always been a bottleneck during IC product sign-off\, regardless of the application. This talk presents a revolutionary approach for creating efficient manufacturing mixed-signal tests that reduce test costs and test escapes. The methodology is called analog scan and requires DfT of a circuit-under-test (CUT) to inject stimulus signals and observe responses. The inserted circuitry is not placed in series with signal propagation paths\, and it is turned off in the mission mode. The control and output of the DfT circuitry is connected to test data registers (TDRs)\, typically placed outside the mixed-signal block under test. \nAnalog scan methodology brings multiple benefits. First\, there is a massive decrease of test cost\, since analog scan tests run orders of magnitude faster than a large majority of spec-based tests on ATE. Analog defect simulation also runs much faster than for spec-based tests. With appropriate automation\, top-level test development is also significantly accelerated. Defect coverage figures achieved with analog scan are usually higher than those obtained with functional tests. Lastly\, analog scan facilitates diagnosis of field returns. \nBiography \nVladimir Zivkovic is a principal product engineer for Analog Mixed-Signal and Defect-oriented Test at Siemens EDA. He graduated from the Faculty of Electrical Engineering at the University of Nis in Former Yugoslavia and obtained PhD in Electrical Engineering from the University of Twente\, the Netherlands. \nHe has more than 20 years of industrial experience in Mixed-signal DfT\, test flow automation\, test coverage analysis and AMS verification. His previous affiliations include Philips Research (Netherlands)\, NXP Semiconductors (Netherlands)\, D4T Systems (small startup company\, Netherlands)\, Nikhef/CERN (Netherlands/Switzerland)\, Cadence Design Systems (Scotland\, UK) and Infineon (Denmark). He is program committee member of IEEE European Test Symposium (ETS) and provided significant contribution during the development of IEEE 2427 standard for Analog Defect Modeling and Coverage. He is also vice chair of IEEE P1687.2 (Analog Test Access standardization) working group. \nDetailsLee Harrison \nDirector of Product Marketing\, Tessent\, Siemens EDA \n×Lee Harrison\nDirector of Product Marketing\, Tessent\, Siemens EDA\nBiography \nLee Harrison is Director\, Product Marketing\, with Siemens Tessent Division. He has over 25 years of industry experience working with Siemens Tessent DFT products\, with a focus on safety and security. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC\, ITC\, VTS\, ETS\, and DATE. \nDetailsBart Keppens \nChief Business Development\, Sofics \n×Bart Keppens\nChief Business Development\, Sofics\nBeyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os \nAs CMOS nodes scale\, designers face a widening gap between core capabilities and system-level requirements. While foundry GPIOs in FinFET and GAA processes typically top out at 1.8V\, many applications still demand 3.3V “Over-Voltage Tolerant” (OVT) interfaces for legacy compatibility and robust system integration. Conversely\, the rise of chiplet architectures introduces the opposite challenge: Die-to-Die (D2D) interfaces that must operate at specialty voltages below the typical GPIO range (1V or lower) to minimize power and maximize speed. \nThis presentation explores the design and ESD protection of these specialty interfaces. We examine the “3.3V in a 1.8V process” dilemma\, focusing on stacking techniques to maintain Safe Operating Area (SOA) during power sequencing and transient events. We then pivot to the unique requirements of chiplet interconnects. Unlike standard I/Os\, D2D interfaces require: (a) Specialized ESD: Traditional >2kV HBM protection is often overkill for D2D\, introducing excessive parasitic capacitance that limits bandwidth. (b) Thin-Oxide Integration: To achieve high speeds\, D2D circuits utilize sensitive thin-oxide transistors that are easily damaged without custom ESD clamps. (c) Area Efficiency: With thousands of required connections\, standard I/O pads consume prohibitive silicon area. \nAttendees will gain a practical framework for specifying and verifying both higher and lower voltage specialty I/Os\, with an emphasis on co-designing circuits and ESD to optimize PPA in modern\, heterogeneous systems. \nBiography \nBart Keppens received an engineering degree in electronics in 1996 and started his career at imec in Belgium. From 2002 he joined Sarnoff Europe\, solving on-chip ESD related problems for customers worldwide. After a management buy-out in June 2009\, Sarnoff Europe became ‘SOFICS – Solutions for ICs’ where Bart is responsible for global business development. Bart (co-) authored more than 40 peer-reviewed published articles on ESD protection. \nDetailsNeel Gopalan \nFounder and CEO Executive Director\, Technical Product Management\, Synopsys \n×Neel Gopalan\nFounder and CEO Executive Director\, Technical Product Management\, Synopsys\nRevolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies \nThe rapid advancement of semiconductor technology necessitates innovative approaches to Analog Layout Synthesis\, a critical aspect in circuit design for FinFET and GAA nodes. This presentation introduces Industry’s First transformative potential of Generative AI (GenAI) and Machine Learning (ML) in automating and optimizing the analog layout process. We will discuss how GenAI can generate high-quality layout designs by learning from vast datasets of existing designs\, while ML algorithms enhance the efficiency of design creation and predictions. Furthermore\, we will delve into the role of AI in facilitating intelligent decision-making throughout the design process\, enabling adaptive responses to design constraints and objectives. By integrating these cutting-edge technologies\, we aim to significantly reduce design time\, improve layout quality\, and foster innovation in analog circuit design. This presentation will provide insights into the methodologies employed\, the challenges encountered\, and the future directions of analog layout synthesis in the context of AI-driven advancements. \nBiography \nNeel Gopalan is an Executive Director\, in the Products and Market group. Neel leads Technical Product Management for AMS tools including Custom Compiler\, PrimeSim and Characterization. Neel has been with Synopsys for the last 20 years; during this time he has been part of Custom Compiler Product Engineering team. He was an integral part of the team that built Custom Compiler along with all the collaterals needed for Custom Design. Neel and his team built industry’s 1st iPDK\, which is now the standard for PDKs in the industry. Neel now leads Analog Design Migration\, ASO and Layout Synthesis. Prior to Synopsys\, Neel worked for Cadence for 5 years \nDigital Design Early Careers SpeakersDetailsDave Sanders \nAssociate Fellow\, Rolls-Royce \n×Dave Sanders\nAssociate Fellow\, Rolls-Royce\nBiography \nDave Sanders is an Associate Fellow at Rolls-Royce specialising in the development of complex electronic hardware. He has 28 years of experience working in the electronics industry\, with 26 of those developing the safety critical microprocessors that form the heart of the Rolls-Royce control systems for both aerospace and non-aerospace applications. \nDave is a member of the European DO254 Users Group since 2012 and has contributed to various regulation working groups including co-authoring AMC 20-152A. He became a Fellow of the IET in 2018 and was awarded the Rolls-Royce Controls Gold Innovation Award in 2015 in recognition of the successful development of the sixth-generation safety critical microprocessor\, which has already accumulated over 30 million fault free flying hours. \nIn his spare time\, Dave is a keen runner and currently Lichfield Running Club Secretary.DetailsHaydn Povey \nFounder and CEO\, SCI Semiconductor \n×Haydn Povey\nFounder and CEO\, SCI Semiconductor\nBiography \nWith over 30 years experience in the technology domain Haydn has unparalleled experience in microprocessor IP\, cyber security\, and real world cyber-physical systems. \nHaving led the introduction of Arm Cortex-M processors he subsequently led the Processor Divisions security technologies\, including TrustZone & SecurCore. \nHe is a founder board member of the IoT Security Foundation. \nDave is a member of the European DO254 Users Group since 2012 and has contributed to various regulation working groups including co-authoring AMC 20-152A. He became a Fellow of the IET in 2018 and was awarded the Rolls-Royce Controls Gold Innovation Award in 2015 in recognition of the successful development of the sixth-generation safety critical microprocessor\, which has already accumulated over 30 million fault free flying hours. \nIn his spare time\, Dave is a keen runner and currently Lichfield Running Club Secretary. \nDetailsMichael O’Sullivan \nEngineering director\, Cadence \n×Michael O'Sullivan\nEngineering director\, Cadence\nBiography \nMichael O’Sullivan is an engineering director at Cadence with a focus on verification and is based in Edinburgh\, Scotland. Michael has been with Cadence for over 27 years with various roles in sales\, marketing and design services. \nPrior to Cadence he was a design engineer at S3 Group in Dublin\, Ireland and at Philips in Eindhoven\, The Netherlands. Michael has an Masters of Engineering Science from the National University of Ireland. \nDetailsLoay Qteet \nStaff Application Engineer\, Synopsys \n×Loay Qteet\nStaff Application Engineer\, Synopsys\nBiography \nLoay Qteet\, Applications Engineering\, Staff Engineer at Synopsys\, with six years of experience in the Electronic Design Automation (EDA) field. He specializes in physical design\, RTLIIGDS flow development\, and EDA applications of Implementation and AI. Loay has played a key role in supporting various customer\, helping them to achieve their goals effectively and ensuring that Synopsys products meet their evolving requirements.DetailsMatt Cossins \nEcosystem Development Manager\, Arm \n×Matt Cossins\nEcosystem Development Manager\, Arm\nBiography \nMatt Cossins is an Ecosystem Development Manager in Arm’s AI and Developer Platforms group\, where he supports the adoption of Arm-powered AI compute platforms through developer education\, enablement\, and collaboration between industry and academia. \nAn alumnus of the UKESF programme\, he holds an MEng in Electrical and Electronic Engineering from the University of Nottingham\, where his thesis focused on neuromorphic AI. He previously held engineering roles at Capgemini\, delivering software and embedded research projects for multiple clients\, and at Cambridge-based cellXica\, where he worked on embedded and RTL design for software-defined radio in 5G communications. \nMatt is a recipient of awards from organisations including the IET\, UKESF\, and Electronics Weekly\, and mentors engineering students through the Arkwright Scholarships Trust.DetailsCatriona Wright \nCo-founder\, Chipletti \n\nModerator \n\n×Catriona Wright\nCo-founder\, Chipletti\nBiography \nCatriona Wright is co-founder of Chipletti\, a Cambridge-based fabless semiconductor startup developing AI accelerators for physical AI systems that require low power\, high performance real-time operation within tight SWaP-C constraints. She works across strategy\, partnerships\, and operations while helping translate emerging AI compute needs into practical hardware solutions. \nCatriona has more than 25 years of experience delivering complex semiconductor products from concept through to production. Her career spans digital design\, program leadership\, and scaling multidisciplinary teams to deliver advanced silicon. Before founding Chipletti\, she held roles at both start-ups and large companies including Riverlane\, DisplayLink\, Cambridge Semiconductor\, TTPCom and Nortel Networks\, leading IC development programmes and coordinating cross-functional engineering teams. \nShe holds a First Class MEng in Electrical and Electronic Engineering from the University of Edinburgh and an MBA from The Open University. Catriona is passionate about building strong deep tech teams and helping grow the semiconductor ecosystem in the UK. She is also active in outreach\, running coding clubs for primary school students and encouraging more young people – particularly girls – to explore engineering. \nDetailsRaj Gawera \nChief Operating Officer\, UK Semiconductor Centre \n×Raj Gawera\nChief Operating Officer\, UK Semiconductor Centre\nBiography \nRaj has over 30 years of experience in the semiconductor field having held senior technical and commercial roles in semiconductor organisations spanning IP\, Fabless and IDM business models. He is now COO of the newly formed UK Semiconductor Centre – with an ambitious plan to strengthen the UK semiconductor ecosystem and grow international partnerships. \nIn his early career\, Raj was part of initial IEEE 802.11 team to define first WLAN standard in 1996 – a technology which has now shipped many billions of units. Raj also helped pioneer the first 3G data transmissions working with Motorola and others to demonstrate one of the first 3G video calls at the 3GSM show in 1998 – many years before 3G licences were awarded. \nRaj was a founder member of 3G technology startup UbiNetics (1999)\, that successfully exited in 2005 for over $120m USD. As part of that deal\, Raj joined CSR and ultimately took the role of VP Marketing where he was part of the team that acquired SiRF Technologies for $136m (2009) to add GPS technology to CSR portfolio. In 2012\, he helped sell CSR’s handset business to Samsung in a deal worth $310m for 310 staff. As part of Samsung\, Raj was promoted to VP heading up the SCSC division leading the silicon and software development for Samsung’s chipsets for over a decade\, providing connectivity technology that shipped in hundreds of millions of Samsung products. \nRaj has held a number of board positions including Chair of Cambridge Wireless and NED for CSA Catapult bringing experience and advice on the global semiconductor market.AwaitingNick McKeown \nProfessor \nAwaitingMahdieh Ghoddusi \nDirector of Delivery\, UKESF
URL:https://techworks.org.uk/event/designing-the-future-analogue-mixed-signal-ams/
LOCATION:Regents University London\, Inner Circle\, Regent’s Park\, London\, NW1 4NS
CATEGORIES:DESN,past-events,TechWorks
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DTSTART;TZID=Europe/London:20260326T140000
DTEND;TZID=Europe/London:20260326T150000
DTSTAMP:20260225T121430Z
CREATED:20260225T121430Z
LAST-MODIFIED:20260225T121430Z
UID:5764-1774533600-1774537200@techworks.org.uk
SUMMARY:IoTSF March Webinar
DESCRIPTION:‘Autonomous Compliance: Operationalising EU CRA and UK PSTI via Embedded Microservices’ and ‘Standards vs. Security: A Proactive Compliance Framework’\nPresentation 1: \nWith the UK PSTI in effect and the EU Cyber Resilience Act (CRA) approaching\, IoT manufacturers face a massive manual burden of vulnerability reporting and lifecycle governance. This session introduces a shift from static documentation to “Autonomous Compliance.” By replacing monolithic firmware with a modular\, microservice-based architecture\, the Microservice Store (MSS) and its integrated Security Manager (iSM) automate mandatory obligations—including SBOM generation\, 24-hour module-level incident notification\, fault-containment\, and targeted security updates. Murat Cakmak will demonstrate how device-level evidence and edge-to-cloud automation transform compliance from an engineering bottleneck into a seamless\, verifiable platform function. \nMurat Cakmak \nMurat is an expert in cybersecurity and computer science and has dedicated his career to addressing the complex challenges of IoT security and development. As the driving force behind Microservice Store\, Murat has been leading the charge in solving chronic security and production issues that have long hindered the IoT industry. Passionate about pioneering secure and scalable IoT solutions\, Murat continues to push the boundaries of what’s possible\, making security an essential and accessible standard for all. \nPresentation 2: \nDetails and bio to follow.
URL:https://techworks.org.uk/event/iotsf-march-webinar/
LOCATION:Webinar
CATEGORIES:IoTSF,past-events,TechWorks
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DTSTART;VALUE=DATE:20260326
DTEND;VALUE=DATE:20260327
DTSTAMP:20260204T134549Z
CREATED:20260204T133431Z
LAST-MODIFIED:20260204T134549Z
UID:5328-1774483200-1774569599@techworks.org.uk
SUMMARY:IMAPS-UK: MicroTech 2026 Conference
DESCRIPTION:IMAPS-UK: MicroTech 2026 Conference at King’s Conference Centre\, Hedge End\, Southampton – Thursday 26th March 2026 and Heterogeneous Integration – Explained! Workshop at University of Southampton on Wednesday 25 March 2026 \nThe IMAPS-UK MicroTech 2026 Conference on Thursday 26th March 2026 at the King’s Conference Centre\, Hedge End\, Southampton will focus on Driving Innovation in Semiconductor Packaging. The preliminary Conference Agenda includes state-of-the-art presentations on the advanced packaging market\, the UK Semiconductor Centre\, advanced packaging technologies including laser based processes\, heterogeneous integration\, interposers and 3D integration. \nMore Information and Registration: https://www.imaps.org.uk/events/microtech-2026-driving-innovation-in-semiconductor-packaging/ \nThe Conference is complemented by a Workshop on Heterogeneous Integration – Explained! On Wednesday 25th March 2026 at the University of Southampton. \nMore Information and Registration: https://www.imaps.org.uk/events/heterogeneous-integration-electronics/ \nPlease contact the IMAPS-UK Office (office@imaps.org.uk ) with any questions.
URL:https://techworks.org.uk/event/imaps-uk-microtech-2026-conference/
LOCATION:Southampton
CATEGORIES:past-events,Promoted
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260325T140000
DTEND;TZID=Europe/London:20260325T150000
DTSTAMP:20260612T121627Z
CREATED:20260120T121646Z
LAST-MODIFIED:20260612T121627Z
UID:4711-1774447200-1774450800@techworks.org.uk
SUMMARY:Women in TechWorks Webinar with Madhuparna Datta
DESCRIPTION:Madhuparna Datta\nVLSI & EDA expert\nMadhuparna is an EDA and VLSI expert with over 25 years semiconductor industry experience\, who has worked across UK\, India and Sweden. She started off with PCB & FPGA design in Telecom at C-DoT\, and then moved to the EDA industry at Cadence Design Systems where she has worked across Silicon-Package-Board as well as Digital Design and Implementation product lines. Currently an AE Director with people management role along with overall technical lead for digital and signoff technical campaigns across the region. She has been involved with CPU\, GPU and system IP designs on all the advanced nodes including 16nm\, 7nm\, 5nm\, 3nm etc. Her passion for STEM made her a SWE Global Ambassador and founder of SWE Cambridgeshire affiliate in September 2022\, the first global SWE affiliate in UK\, which helps provide networking and professional development opportunities for local engineers. She has been elected to the SWE senate for FY26-28. Mentoring engineers along their career path led to her winning the Electronics Weekly “Women Leaders in Electronics Awards 2024” for ‘Mentor of the year’ along with being finalist for ‘Leader of the year’ and ‘Woman of the year’. She was invited by UK Department of Science\, Innovation and Technology (DSIT) to be part of the UK semiconductor delegation to India in March 2025 in recognition of her industry expertise. She is currently a trustee on the UKESF board due to great alignment on values and approaches towards encouraging more young people to study Electronics.
URL:https://techworks.org.uk/event/women-in-techworks-webinar-with-madhuparna-datta/
LOCATION:Webinar
CATEGORIES:past-events,TechWorks,WITW-Past Event,Women in TechWorks
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260319T140000
DTEND;TZID=Europe/London:20260319T160000
DTSTAMP:20260312T201430Z
CREATED:20260217T123403Z
LAST-MODIFIED:20260312T201430Z
UID:5621-1773928800-1773936000@techworks.org.uk
SUMMARY:In-Cabin Sensing: Accelerating NCAP Compliance through Simulation
DESCRIPTION:A workshop on in-cabin scenario prioritisation\, NCAP protocols\, sensor modelling and simulation-based testing.Join the Sim4CAMSens2 project team on 19 March for an interactive workshop focused on the “red thread” of NCAP compliance. This is an exciting online workshop showcasing our latest in-cabin simulation progress and we need your expertise to shape what comes next. \nWe want to hear from developers\, buyers\, and integrators to identify the real-world pain points of physical testing and help prioritise critical Driver Monitoring and Occupant Monitoring System scenarios. Through live polling and breakout discussions\, your input will directly influence the development of repeatable simulation protocols for the next generation of vehicle safety. \n\n\n\n\nTIME\nDETAILS\n\n\n\n\n14:00\nWelcome \nIntroduction to the workshop\, objectives\, and agenda \nGunny Dhadyalla: Network Director\, AESIN\n\n\n14:05\nProject Overview: Simulation for Safer Cabin System \nOverview of the S4CS projects\, highlighting how simulation supports the development and validation of in-cabin sensing systems aligned with NCAP requirements. \nGunny Dhadyalla: Network Director\, AESIN\nDavid Briant : AV Product Manager\, Claytex\n\n\n14:15\nSensor Simulation Technologies \nDiscussion on sensor modelling\, virtual testing environments\, and the benefits of simulation for accelerating in-cabin sensing development. \nDr. Eliott London: Simulation Performance Engineer\, rFpro\nDavid Briant : AV Product Manager\, Claytex\n\n\n14:30\nScenario Development \nSimulation scenarios for Driver Monitoring Systems (DMS) and Occupant Monitoring Systems (OMS) aligned with NCAP protocols. \nDr. Eliott London: Simulation Performance Engineer\, rFpro\nGraham Lee: Principal Engineer\, SysElek\n\n\n14:40\nInteractive Poll\n \nParticipants vote on priority NCAP in-cabin sensing scenarios. \n\n\n\n14:45\nBreakout Discussions\n \nInteractive discussions on industry challenges\, validation needs\, datasets\, and opportunities for simulation in in-cabin sensing. \n\n\n\n15:30\nBreakout Feedback \nGroups share key insights and discuss common industry priorities. \n\n\n\n15:50\nConclusions and Next Steps \nSummary of key takeaways and future collaboration opportunities. \nGunny Dhadyalla– AESIN\n\n\n\n\nSpeakersDr. Elliot London\nSimulation Performance Engineer\, rFpro \nDr. Elliot London is Simulation Performance Engineer at rFpro – the leading simulation environment for development and testing of ADAS and autonomous vehicles. Elliot’s background is in physics and telecommunications engineering where he specialized in quantifying the accuracy of complex physical models and digital twins during his PhD. As a member of rFpro’s expert team\, Elliot leverages his expertise to develop and evaluate camera sensor models and to verify the accuracy of rFpro’s simulations for safety-critical ADAS and AV applications. \nDavid Briant\nAV Product Manager\, Claytex \nAfter graduating from Oxford Brookes\, David started at Claytex in 2015. Specialising in vehicle system modelling and multibody dynamics\, he worked in the team that developed VeSyMA suite of vehicle simulation libraries. He has experience in a variety of industries but predominantly in automotive and motorsport. In 2025 he transitioned to managing Claytex’s Autonomous Vehicle team who develop LiDAR and Radar sensor models and scenario control within rFpro’s AV elevate\, one of the highest fidelity autonomous vehicle simulation platforms on the market. \nDr. Graham Lee\nPrincipal Engineer\, Syselek \nGraham is a systems engineer with over 15 years’ experience working in industry and academia. He has specialist knowledge and expertise in the design\, development\, and testing of automated driving systems for on- and off-road applications. He has developed cooperative CAV applications in automotive (passenger car and mass transit)\, manufacturing (logistics)\, and agri-tech sectors.
URL:https://techworks.org.uk/event/in-cabin-sensing-accelerating-ncap-compliance-through-simulation/
LOCATION:Webinar
CATEGORIES:AESIN,past-events,TechWorks
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DTSTART;TZID=Europe/London:20260319T140000
DTEND;TZID=Europe/London:20260319T143000
DTSTAMP:20260224T171809Z
CREATED:20260224T171809Z
LAST-MODIFIED:20260224T171809Z
UID:5756-1773928800-1773930600@techworks.org.uk
SUMMARY:TechWorks AI Webinar with Bill Bauman
DESCRIPTION:Cybersecurity and governance for agentic AI\nA general overview of several elements of computational trust in the emerging era of Agent-Based Software and how Agent Vault addresses many core aspects of it. \nWe’ll discuss LLMs\, agentic memory systems\, RAG data\, cryptographically signed tools\, policy access\, human-in-the-loop\, and more. \nSome topics will be discussed within the context of demonstrating how Agent Vault implements the solution. We’ll also have an open conversation for questions\, feedback\, and group input. \nBill BaumanCo-founder and CEO\,  Ntur AI \nBill is the co-founder and CEO of Ntur AI\, a company focused on Agentic AI security and governance. He’s passionate about product development and delivery\, product-market fit\, and AI security. Bill’s background draws from a varied history of hands-on technical roles\, architecture\, marketing\, and product management.
URL:https://techworks.org.uk/event/techworks-ai-webinar-with-bill-bauman/
LOCATION:Webinar
CATEGORIES:past-events,TechWorks,TechWorks AI
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260227T140000
DTEND;TZID=Europe/London:20260227T160000
DTSTAMP:20260224T100834Z
CREATED:20260223T164525Z
LAST-MODIFIED:20260224T100834Z
UID:5743-1772200800-1772208000@techworks.org.uk
SUMMARY:Design and Verification of Silicon Chips
DESCRIPTION:Join us at the University of Oxford\, Thom Building\, Engineering Science Department\, Oxford OX1 3PJ\nWhether you’re curious about chip design\, interested in quality assurance\, or simply want to understand what happens before a processor hits the market. Come along to: \n\nConnect with the semiconductor industry\nLearn about career opportunities in verification and related fields\nSpeak to industry professionals and experts in the field\n\nOpen to network professionals and all staff and students. We especially welcome students from Physics\, Materials\, Computer or Engineering Sciences and Maths. \nNote\, there is no registration\, please just pop along on the day.
URL:https://techworks.org.uk/event/design-and-verification-of-silicon-chips/
LOCATION:University of Oxford\, Parks Road\, Oxford\, OX1 3PJ
CATEGORIES:past-events,Promoted,TechWorks,Women in TechWorks
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260226T140000
DTEND;TZID=Europe/London:20260226T150000
DTSTAMP:20260220T183957Z
CREATED:20260220T183957Z
LAST-MODIFIED:20260220T183957Z
UID:5734-1772114400-1772118000@techworks.org.uk
SUMMARY:IoTSF Webinar: Quantum Safety in IoT
DESCRIPTION:The rapid proliferation of IoT devices across critical industries – e.g. automation\, healthcare\, smart cities – has introduced significant security challenges. Whilst current cryptographic protocols safeguard data today\, upcoming developments in quantum computing threaten to render these protections obsolete. And this threat is amplified by the actions of adversarial nation states looking to disrupt critical industries whilst engaging in hybrid warfare. \nThis presentation explains the implications of quantum computing on IoT ecosystems. \nBy the end of the session\, participants will have an understanding of quantum safety\, what it means for IoT\, and a sensible timeline of future actions. \nSteven Kennedy is a seasoned cybersecurity architect with deep expertise in securing some of the most complex networks in the world (e.g. Tier 1 telecoms\, hyperscale public cloud). After working for several years in Microsoft cybersecurity product management\, he took the plunge to become a self-employed consultant. Working with Blue Mesh Solutions\, he’s focused on using his knowledge of cryptography and quantum mechanics to help clients transition smoothly into the post-quantum future. \nRichard Brooks sent the first IoT hello world message as ‘hello 5G’ across a private 5G network in the UK. \nThis was all part of the UK Government’s 5G Accelerator Programme and involved collaborators from Hutchinson Ports\, 3 Telecom\, University of Cambridge\, the Port of Felixstowe and Blue Mesh Solutions. Exploratory use cases were developed including autonomous port haulage vehicles and our IoT based project to create digital twins of the large quayside container cranes. \nCritical strategic assets\, such as ports\, require hardened IoT estate encryption\, and testing new encryption technologies to present a harder\, quantum safe cryptography stance became the final outcome of the project\, leading to new quantum safe MQTT solutions and a best in class commercial partnership.
URL:https://techworks.org.uk/event/iotsf-webinar-quantum-safety-in-iot/
LOCATION:Webinar
CATEGORIES:IoTSF,past-events,TechWorks
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