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X-WR-CALDESC:Events for TechWorks
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DTSTART;VALUE=DATE:20260416
DTEND;VALUE=DATE:20260417
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UID:4805-1776297600-1776383999@techworks.org.uk
SUMMARY:FPGA Frontrunners @ Microchip
DESCRIPTION:CLICK HERE to find out more about the FPGA Frontunners group \n\nField Programmable Gate Arrays (FPGAs) play a critical role in modern electronic systems\, powering applications that range from everyday consumer products to mission-critical infrastructure. Their ability to be customized and reconfigured after deployment makes them uniquely valuable in fast-moving technology environments. At the same time\, this adaptability introduces distinct security challenges that must be carefully addressed. \nBecause FPGAs can be reprogrammed in the field\, they present a broader attack surface than fixed-function hardware. Threats targeting configuration data\, intellectual property\, firmware integrity\, and runtime behavior can compromise not only the device itself\, but also the larger systems that rely on it. As FPGAs are increasingly used to support advanced workloads—including data-intensive and intelligent processing—security risks continue to grow in both scope and impact. \nEffective FPGA security extends beyond physical protection. It encompasses the full lifecycle and ecosystem surrounding the device\, including design tools\, bitstreams\, firmware\, software interfaces\, and data flows. In systems that incorporate adaptive or AI-assisted functionality\, ensuring trust\, integrity\, and resilience across this ecosystem is especially critical. \nThis event explores the evolving landscape of FPGA security\, highlighting emerging threats\, recent advances\, and proven mitigation strategies. Through expert insights and real-world case studies\, the program aims to equip engineers\, researchers\, and security professionals with practical guidance for securing FPGA-based systems today and in \nknowledge\, techniques\, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so. \nWho Should Attend\n\nFPGA Designers and Engineers\nSystem Architects\nSafety and Security Specialists\nSupply Chain Professionals\nIndustry Regulators and Standards Bodies\n\nWhy Attend? \n\nGain insights from leading experts on the evolving risks and mitigation strategies\nLearn how to meet functional safety and security requirements across multiple industries\nNetwork with industry peers and potential collaborators\nParticipate in discussions on best practices\, regulatory trends\, and real-world case studies\n\nAgenda\n\n\n\n\nTime\nDetails\n\n\n\n\n10:00\nRegistration\n\n\n10:30\nMicrochip Secure FPGA’s\nIan Pearson\nPr. ESE\, Microchip\n\n\n11:00\nA Visual Demonstration of True Random Numbers from a Quantum Computer\nPhill J Payne\nPrincipal Digital Design Engineer\, Novomorphic\n\n\n11:30\nAre FPGAs unique for security?\nMartin Thompson\nSenior Technical Specialist\, ZF Engineering Solutions\n\n\n12:00\nBeyond Bitstream Encryption: FPGA Security for High-Assurance Systems\nDaniel Tee\nSenior Firmware (FPGA) Engineer\, Leonardo\n\n\n12:30\nNetworking Lunch\n\n\n13:30\nOverview of prEN50767 : CRA Vertical Standard for FPGA/ASIC\nPeter Trott\nStaff FAE\, Microchip\n\n\n14:00\nHardware-Rooted Bitstream Security\nMans Ahmadian\nChief Innovation Officer\, Sundance\n\n\n14:30\nWrap Up\n\n\n14:45\nClose\n\n\n\n\nSpeakersDetailsPhill J Payne \nPrincipal Digital Design Engineer\, Novomorphic \n×Philip Payne\nPrincipal Digital Design Engineer\, Novomorphic\nPresentation: A Visual Demonstration of True Random Numbers from a Quantum Computer \nTrue randomness is one of those things everyone assumes they have… right up until security\, trust\, or assurance actually matters.\nThis session reveals a practical way to pull physical entropy from a real quantum computer and inject it into FPGA and embedded systems as a usable\, engineering-grade input. You’ll see quantum behaviour turned into something tangible and immediate — a live “quantum dice” demonstrator that makes the invisible visible — and you’ll learn why this matters far beyond novelty. \nWe’ll explore what changes when your randomness isn’t “noisy enough” pseudo-random\, but rooted in genuine physical uncertainty\, and how that can reshape thinking around key generation\, nonces\, reseeding\, and trusted system design. A live comparison between simulation and real quantum hardware draws a clear line between “looks random” and “is random”. \nIf you build secure edge systems and care about trust boundaries\, this will change how you think about entropy. \nBiography \nPhill J Payne is Principal Digital Design Engineer at Novomorphic\, specialising in secure\, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines\, reduces memory pressure\, and delivers high-performance vision and inference at the edge. Across 26 years\, Phill has turned novel architectural ideas into deployable systems under tight power\, latency\, throughput\, and reliability constraints\, with deep experience in security-grade FPGA development and signal-processing workloads. Previously\, he delivered end-to-end FPGA firmware and software for advanced systems\, including a patented communications technique designed to operate in contested jamming environments\, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games\, translating complex engineering into practical tools. \nCloseDetailsMartin Thompson \nSenior Technical Specialist\, ZF Engineering Solutions \n×Martin Thompson\nSenior Technical Specialist\, ZF Engineering Solutions\nPresentation: Are FPGAs unique for security? \nIn this talk we will investigate the degree to which systems containing programmable logic (including FPGAs) can be considered “unique” in their security requirements and implementation options\, when compared to more conventional microcontroller and desktop processor systems. \nWe will briefly define what we mean by “security” in this context (both in terms of market requirements and attacker motivations) and what primitives can be used to achieve it. A review of the variety of potential attacks will be presented and we will spend some time on the peculiarities of FPGA-based systems by comparing them directly with other implementation strategies. Finally\, we will conclude with an answer to the question posed in the title. \nBiography \nMartin Thompson is a Senior Technical Specialist at ZF Engineering Solutions. He has spent over 30 years developing systems and algorithms for products in the automotive and aerospace domains. He enjoys working across the full range of software and electronics disciplines\, from desktop algorithm development to microcontroller\, DSP and FPGA code as well as electronic design\, PCB layout (and when the need arises\, soldering!). He specialises in optimisations of whole electronic systems\, based on a detailed understanding of the trade-offs across multiple domains. Particular highlights have included the development of very low-cost FPGA-based imaging and radar-systems. \nSince 2015\, Martin has been heavily involved in the cybersecurity of embedded systems and is currently the technical leader of an penetration-testing team with an embedded-system focus. He contributes to the Internet of Things Security Foundation Assurance Framework\, the Automotive Threat Matrix\, and is a member of the MITRE hardware CWE SIG and the CWE-RTL working group. Finally\, he spends some of his time researching novel side-channel attacks in pursuit of a PhD\, with the University of Durham. \nCloseDetailsIan Pearson \nPr. ESE\, Microchip Technology Inc. \n×Ian Pearson\nPr. ESE\, Microchip Technology Inc.\nPresentation: Leveraging Microchip Secure FPGAs \nThe foundation of a secure end product lies in the right choice of components. CRA requires a ‘Secure by Design’ approach to product development and support throughout the lifecycle. Microchip FPGA’s have a long history of secure FPGA’s designed to meet the most demanding of military applications but available to all \nBiography \nIan Pearson is a Principle Embedded Solutions Engineer with Microchip Technology covering FPGA\, Security and IoT. He is also the chair of the IoT Security Foundation – Security Assurance Framework Working Group.CloseDetailsMans Ahmadian \nChief Innovation Officer\, Sundance \n×Mans Ahmadian\nChief Innovation Officer\, Sundance\nPresentation: Hardware-Rooted Bitstream Security and Secure Manufacturing Workflow \nA Defense-Grade Implementation Using PolarFire FPGA on Sundance PCIe104N Platform As FPGAs become central to mission-critical defense and aerospace systems\, the security challenge has shifted. It is no longer enough to protect configuration data in the fi eld; we must also secure it during manufacturing\, programming\, testing\, and across the entire supply chain. When production is distributed across multiple facilities and third-party partners\, the FPGA bitstream becomes a high-value target\, vulnerable to interception\, overbuilding\, hardware substitution\, or reverse engineering. This talk presents a defence-grade secure provisioning workflow implemented on the Sundance PCIe104N platform\, built around the PolarFire MPF500T FPGA\, and explains how it establishes trust from silicon to system deployment. \nAt the heart of this approach is hardware-rooted security. PolarFire devices generate a unique\, silicon-derived identity using Physically Unclonable Functions (PUFs)\, meaning that no two FPGAs are electrically identical and no identity can be copied or cloned. During secure provisioning\, this identity is validated before any sensitive key material is transferred. The customer’s encrypted bitstream and User Encryption Key are generated inside their own trusted environment and securely delivered for programming using Microchip’s Secure Production Programming Solution. If authentication fails at any stage\, such as in a dummy FPGA impersonation attempt\, the process stops immediately. No keys are exposed\, and no firmware is released. What this workflow ultimately provides is confidence. Confidence that the hardware being programmed is genuine. Confidence that only the approved number of boards can ever be provisioned. Confidence that the bitstream cannot be intercepted\, modified\, or extracted through side-channel attacks. By combining controlled manufacturing\, independent validation\, hardware security modules\, authenticated encryption\, and built-in DPA countermeasures\, Sundance ensures customers receive fully tested\, securely programmed boards\, without any risk of supply-chain compromise or intellectual property leakage. Today\, I will walk you through how this architecture works and why it sets a scalable model for secure FPGA manufacturing. \nBiography \nMans Ahmadian serves as the Chief Innovation Officer at Sundance\, where he leads the architecture of next-generation\, high-density AI Systems-on-Modules (SoMs). In this role\, he directs the design of specialized AI Engines and systems otimized for low-power\, high-throughput inference in rugged environments. He is instrumental in bridging the gap between AI frameworks and SundanceDSP hardware. Additionally\, his work ensures the reliability of autonomous Edge AI platforms in mission-critical settings by optimizing SWaP (Size\, Weight\, and Power) solutions and integrating safety-critical\, “fail-safe” R&D workflows. \nThroughout his career\, he has been granted numerous patents for his innovations in image processing\, advanced camera systems and imaging sensor operations. His technical and commercial achievements have earned him several prestigious honors\, including the IET (Institute of Engineering and Technology) Innovation Award in software development\, the SMART::SCOTLAND Innovation Award\, and a Business Plan Competition win. These accolades are supported by a robust academic foundation\, including a PhD in Medical Image Processing\, an MSc in Biomedical/Medical Engineering\, and a BSc in Electronics from The University of Edinburgh\, and postgraduate certificates in Health Data Science and Big Data and AI. \nCloseDetailsPeter Trott \nStaff FAE\, Microchip Technology Inc. \n×Peter Trott\nStaff FAE\, Microchip Technology Inc.\nPresentation: Overview of prEN50767 : CRA Vertical Standard for FPGA/ASIC \nThe EU CRA requirements can be met via a presumption of conformity using horizontal and vertical harmonised standards. These standards are in development and will release very close to the enforcement date. In this session we will give some insight into what is coming in the vertical standard for FPGA/ASIC. The prEN50767 standard provides the requirements for FPGA/ASIC vendors to meet the Important Class I categorisation of FPGA/ASIC in the EU CRA. \nBiography \nPeter Trott is a Staff Applications engineer at Microchip with over 30yrs experience in the FPGA sector. He has extensive experience in both military and industrial design using FPGA’s. Peter is also a key member of the EU TC47x WG4 Trusted Silicon work group for FPGA/ASIC who are creating the prEN50767 harmonised standard relative to the Important Class I FPGA/ASIC with security features \nCloseDetailsDaniel Tee \nSenior Firmware (FPGA) Engineer\, Leonardo. \n×Daniel Tee\nSenior Firmware (FPGA) Engineer\, Leonardo.\nPresentation: Beyond Bitstream Encryption: FPGA Security for High-Assurance Systems \nField programmable gate arrays (FPGAs) are increasingly deployed in systems where failure or compromise is not an option – from defence and aerospace to critical infrastructure and advanced industrial platforms. In these high assurance environments\, security requirements extend beyond the protections normally offered by device vendors. Engineers must consider the broader context of threats\, deployment conditions\, and system level risk. \nBiography \nDaniel Tee is a Senior Firmware (FPGA) Engineer at Leonardo\, working within the product security team. He joined Leonardo as a graduate in 2022 after completing an integrated MEng in Electronics and Computer Science at the University of Edinburgh\, where he focused on a number of cybersecurity modules in his final year. Daniel now applies his interest in hardware security to developing robust FPGA‑based security solutions for customer‑driven\, mission‑critical applications. \nClose
URL:https://techworks.org.uk/event/fpga-frontrunner-microchip/
LOCATION:Microchip\, 720 Wharfedale Rd\, Winnersh\, Wokingham\, RG41 5TP
CATEGORIES:DESN,past-events,TechWorks
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260423T140000
DTEND;TZID=Europe/London:20260423T150000
DTSTAMP:20260410T152118Z
CREATED:20260326T114231Z
LAST-MODIFIED:20260410T152118Z
UID:6249-1776952800-1776956400@techworks.org.uk
SUMMARY:IoTSF Webinar: CRA Reporting Obligations with Mustanir Ali (Element)
DESCRIPTION:
URL:https://us06web.zoom.us/webinar/register/WN_Lg_DkdFZSx-6TwSdFY5Hxg#/registration#new_tab
CATEGORIES:IoTSF,past-events,TechWorks,Webinar
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260423T160000
DTEND;TZID=Europe/London:20260423T163000
DTSTAMP:20260612T121430Z
CREATED:20260302T111641Z
LAST-MODIFIED:20260612T121430Z
UID:5828-1776960000-1776961800@techworks.org.uk
SUMMARY:How to move from Individual Contributor to Leader in a Male Dominated Environment: A Women in TechWorks Fireside Chat
DESCRIPTION:Our speaker will be talking from two perspectives – firstly her own experience moving into leadership\, and secondly as a leader what I look for in high potential juniors and the behaviours that are helpful \nBiography \nEllie Bramer is an Engineering Manager at Arm\, where she leads multiple teams of software engineers at the intersection of advanced computing\, AI\, and ecosystem innovation. With a background as a systems engineer in the defence sector she has built her career in male-dominated environments\, progressing from individual contributor to experienced engineering leader. Ellie is passionate about building high-performing technical teams and creating pathways for more women to thrive and advance in engineering and tech fields.
URL:https://techworks.org.uk/event/how-to-move-from-individual-contributor-to-leader-in-a-male-dominated-environment-a-women-in-techworks-fireside-chat/
LOCATION:Webinar
CATEGORIES:past-events,TechWorks,WITW-Past Event,Women in TechWorks
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260429
DTEND;VALUE=DATE:20260430
DTSTAMP:20260413T090240Z
CREATED:20260413T090240Z
LAST-MODIFIED:20260413T090240Z
UID:6389-1777420800-1777507199@techworks.org.uk
SUMMARY:Application-Specific Processors (ASIPs) for Physical AI
DESCRIPTION:
URL:https://www.synopsys.com/webinars/application-specific-processors-asip-physical-ai.html?utm_source=techworks&utm_medium=link&utm_campaign=sip_processor-ip&utm_content=asips-pysical-ai-wbnr_link_mul_wbn&tags=Webinars#new_tab
CATEGORIES:Member Event,past-events,Promoted
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/04/NEW-Techworks-site-featured-images-2026-04-13T095807.869.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260430
DTEND;VALUE=DATE:20260501
DTSTAMP:20260410T153442Z
CREATED:20260410T151856Z
LAST-MODIFIED:20260410T153442Z
UID:6384-1777507200-1777593599@techworks.org.uk
SUMMARY:Marvell: Accelerating Interposer Design with Early Signal Integrity Analysis
DESCRIPTION:In this webinar\, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early\, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated\, compute intensive 3D FEM cycles during development\, Marvell uses a Method of Moments (MoM) early SI check available within Synopsys 3DIC Compiler to evaluate routing with real parasitics and simulation data\, fast enough to support rapid iteration and safer exploration of auto routing strategies. Marvell will also share practical correlation takeaways\, where MoM tracks FEM strongly and where additional margin and correlation work may be needed ahead of final signoff.
URL:https://techworks.org.uk/event/marvell-accelerating-interposer-design-with-early-signal-integrity-analysis/
CATEGORIES:Member Event,past-events,Promoted
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260430
DTEND;VALUE=DATE:20260501
DTSTAMP:20260410T152849Z
CREATED:20260408T100947Z
LAST-MODIFIED:20260410T152849Z
UID:6357-1777507200-1777593599@techworks.org.uk
SUMMARY:Synopsys: Powering 3D Multi-Die Designs with RedHawk-SC Electrothermal
DESCRIPTION:
URL:https://www.synopsys.com/webinars/powering-3dic-systems-redhawk-sc-electrothermal.html?utm_source=techworks&utm_medium=link&utm_campaign=mds&utm_content=redhawk-sc-for-multi-die-designs_link_mul_wbn&tags=Webinars#new_tab
CATEGORIES:Member Event,past-events,Promoted
ATTACH;FMTTYPE=image/webp:https://techworks.org.uk/wp-content/uploads/2026/04/NEW-Techworks-site-featured-images-2026-04-08T110634.323.webp
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