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IoTSF Virtual Conference 2021

Webinar

3 -4th NOVEMBER 2021

The Annual IoTSF Conference has built a loyal global following from the IoT stakeholder communities and is renowned for delivering high quality conference programmes.

Building a Trusted AI-based System: Linking the Parts

Webinar

8th NOVEMBER 2021

NMI Electronic Systems Design Group presents a Series of 3 Webinars: Building a Trusted AI-based System. In this second webinar we focus on the communications infrastructure needed when building a trusted AI-based system. This includes the need for secure, robust communications which meet performance requirements for speed and latency both at the edge and with the cloud.

SEMICON EUROPA

ivi

16-19th NOVEMBER 2021

SEMICON Europa attracts a highly influential audience from every segment and sector of the European microelectronics industries including semiconductors, LEDs, MEMS, printed/ organic/ flexible, and other adjacent markets. Exhibitor and attendees meet to enact change and address industry-shaping trends.

NMI Semiconductor Meet & Greet Event

Holiday InnThe Coldra, Newport, United Kingdom

24th NOVEMBER 2021

NMI are delighted to announce the first of our NMI Meet & Greet Events will be held on 24th of November at the Holiday Inn.
This will be the first NMI face to face event we have hosted in over two years and we are looking forwarded to welcoming everyone back.

IMAPS-UK: IPOWER 3 – ELECTRONIC PACKAGING FOR NET ZERO

University of WarwickGibbet Hill Road, Coventry, United Kingdom

2nd DECEMBER 2021

Achieving Net Zero will present some of the most significant challenges to be faced by a wide range of electrical and electronic based industries in the next decade. Getting reliable and fully functional products to market will require electronic and electrical packaging solutions that can operate at higher currents and voltages, faster frequencies and increased temperatures.

Cadence Techtalk: How to Improve Your Chip Design Performance and Productivity Using Machine Learning

Webinar

8th DECEMBER 2021

Machine learning combined with distributed computing offers new capabilities to automate and scale RTL-to-GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects. During this webinar, we will explain key technologies behind the new Cadence ® Cerebrus™ Intelligent Chip Explorer and the RTL-to-signoff implementation flow to show how they can help you achieve up to 10X productivity and 20% PPA improvements for implementation.

Cadence Connect: Club Formal Europe 2021

Webinar

9th DECEMBER 2021

Ready to learn and share ideas about the latest formal verification best practices? Don’t miss this chance to extend your verification expertise and broaden your learning about the latest advances in the field. With the opportunity to hear from members of the Cadence® Jasper™ R&D team about the technology, roadmap, and use cases, be sure to attend this digital event.