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FPGA Frontrunner Meet and Greet

March 29, 2023 @ 9:00 am - 4:30 pm
TechNES is pleased to announce the next FPGA Front Runners event – to he hosted by Leonardo at their venue in Edinburgh on March 29th, and will focus on FPGA Design using High Level Languages.

The FPGA Front runners is all about bringing together the UK FPGA & ASIC design communities to discuss all things gate array. Share knowledge, find out what is going on and network with like-minded people.

This event continues the theme of hosting at a member site, and allowing us more space for networking. There will be a mini expo with members promoting their products and services to the group.

We are also inviting students from across the UK to the event, to bring them closer to the community, for them to understand about the world of FPGAs and meet our members who are actively seeking graduates.

Looking for Accommodation?

The Village Edinburgh Hotel is directly opposite Leonardo and boasts a Pub & Grill, Starbucks, Swimming pool and state-of-the-art gym.  To find out more and book,  visit their website:

https://www.village-hotels.co.uk/edinburgh

Speakers

Padrig Guillard, Sales Account Manager, reflex ces

With nearly 15 years of experience in the FPGA market and a Hardware engineer background, Padrig provides sales and technical to his customers in various high-end applications and markets.

Presentation: Overview of JESD204B/C implementation in FPGA SoM

Key Points:
• Evolution of JESD204B/C support in reflex ces SoM products
• How reflex ces allow JESD204B/C prototyping to reduce design risks and time to market

Iain Pearson, Pr. ESC, Microchip Technology Inc.

Principle Embedded Solutions Engineer at Microchip Ltd covering FPGA, IoT, Security and Cloud applications. Ian has been with Microchip for 23years covering everything from 8bit thro the introduction of the 16bit, 32bit networking and wireless products. He managed the Wireless and Networking function team in Europe where he was an advocate of Secure by Design best practices. In the post covid era and the acquisition of Microsemi the opportunity to join the FPGA team arose allowing him to step back 25 years into his youth and re-discover FPGA all over again.

Presentation: SmartHLS - C++ to Verilog Toolsuite

High Level Synthesis tools can provide a significant improvement in productivity over RTL. This is especially the case in systems employing both a processor core and software in combination with FPGA logic. In this session we will look at where the Microchip SmartHLS toolsuite can be best a utilised to gain most benefit and where it is best to leave code running in software

Daniel Ogilvie, Managing Director, SingMai Electronics

Daniel Ogilvie has over 40 years’ experience designing video products, from no-compromise broadcast quality analogue video decoders and encoders, to forensic image analysis products which can still be occasionally glimpsed on the CSI television programs. Daniel has worked for companies, large and small, in the UK, Canada, Thailand and Singapore. Daniel is a senior member of the IEEE. Outside of work, Daniel Ogilvie is the author of three novels and has a Master's degree in Art History.

Presentation: Moving from Altera to Efinix FPGAs.

Key Points:

  • The motivation for change – cannot buy Altera FPGAs – trying to buy dodgy parts from China.
  • Moving our designs to Efinix – changes needing to be made.
  • Changing the mindset – instantiating the PLLs and assigning pins.

Noah Donaldson, Chief Technical Officer, Annapolis Micro Systems

Noah Donaldson is Chief Technical Officer of Annapolis Micro Systems. Noah has worked at Annapolis for over 20 years in several engineering capacities and in business development. Noah has most recently guided the technical direction and product development of Annapolis’ industry-leading 100GbE EcoSystem that is aligned with the SOSA™ Standard. He holds a Physics BS from Carnegie Mellon University.

Presentation: New Technologies & Architectures Solving EW & SIGINT Challenges

Ben Marshall, Principal Firmware Engineer, Leonardo

Ben is a Principle Firmware Engineer within the Advanced Targeting Firmware Team at Leonardo. He works closely with algorithm designers in the Systems Team to implement complex processing functions on FPGAs across multiple projects. Ben has a particular interest in High Level Design and Model Based Design and enjoys driving forwards best practice in these areas.

Presentation: Model Based Design for FPGAs with Matlab & Simulink

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