CadenceTECHTALK Series: Adopting a Faster, More Efficient Path to Multi-Chiplet Design

With the increasing popularity of multi-chiplet designs that address Moore’s law slowdown and reticle size limitations, leading foundries are offering multiple advanced packaging and die stacking options for different applications.

EDA companies have had to innovate to provide integrated and IC-centric tools while building accurate system-level models to find the fastest and most efficient path for 3D-IC design and analysis.

In this four-part CadenceTECHTALK series, learn how to properly plan and implement stacked digital SoCs, analog/mixed-signal designs, and entire 2.5-D/3-D systems, including meeting system-level power and thermal analysis requirements through an integrated 3D-IC solution.