Cadence Techtalk: How to Improve Your Chip Design Performance and Productivity Using Machine Learning

New applications and technology are driving demand for even more compute power and functionality in the devices we use every day. This has resulted in the semiconductor industry experiencing strong growth based on technology like 5G, autonomous driving, hyperscale compute, industrial IoT, and many others. System-on-chip (SoC) designs are quickly migrating to new process nodes and rapidly growing in size and complexity. Unfortunately, engineering teams are becoming overloaded and cannot keep up with ever-increasing design starts. 

Machine learning combined with distributed computing offers new capabilities to automate and scale RTL-to-GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects. During this webinar, we will explain key technologies behind the new Cadence® Cerebrus™ Intelligent Chip Explorer and the RTL-to-signoff implementation flow to show how they can help you achieve up to 10X productivity and 20% PPA improvements for implementation.