Synopsys: Step-by-Step Guide for Your UCIe Design Verification

As traditional Moore’s law scaling approaches its physical limits, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one way for engineers to pack more functionality into silicon chips and improve yield without affecting fabrication feasibility or project budgets.

The Universal Chiplet Interconnect Express (UCIe) standard was introduced in March of 2022 to help standardize die-to-die connectivity in multi-die systems. UCIe can streamline interoperability between dies on different process technologies from various suppliers. However, multi-die system’s complexity drives the need for a high quality verification process by utilizing Protocol verification IPs and hardware-based verification solutions to achieve great levels of quality in SoCs.

This Synopsys webinar explains various multi-die design types, UCIe multi-die design verification challenges, and how Synopsys verification solutions helps in overcoming these challenges.