Synopsys: Achieving Consistent RTL Power Analysis Accuracy

Register Transfer Level (RTL) power analysis, performed early in the design cycle, is a key component of end-to-end methodology to maximize energy efficiency. Such analysis has become a critical requirement for many IC designs today and in the future. Although RTL power analysis technology has been available to designers for many years, traditional approaches have relied on heuristic methods – thus lacking consistent accuracy. This webinar, presented by Alexander Wakefield, Synopsys Scientist, will focus on Synopsys RTL power analysis technology and best practices that achieve consistent accuracy in the design flow.

First, the motivation for RTL power analysis will be briefly outlined in the context of the overall methodology. Next, the basics of power consumption and associated calculations will be reviewed. Following that, several key factors affecting RTL power accuracy will be examined: fast synthesis and mapping, clock tree modeling, and parasitics estimation. These factors will also be compared with heuristic methods, and finally, some of the best practices to achieve good correlation and consistent accuracy will be covered.

Presenter:
Alex Wakefield is a Synopsys Scientist, with degrees in Engineering and Computer Science from the University of Adelaide, Australia. He has worked for more than 20 years in many areas including Synthesis, Simulation, SystemVerilog, UVM, Constraints, Coverage closure, and Embedded-Software. He has presented papers at many conferences and holds multiple patents. The last few years Alex has primarily been focused Power-Estimation, Leading the Synopsys global rollout of Power-Estimation with Zebu. He is involved in all Synopsys Power-Estimation engagements worldwide.

*This webinar is in partnership with SemiWiki and Synopsys*